Ross Thompson
d8ab7a5de2
Partially working icache.
...
The current issue is a StallF is required to halt the icache from getting an updated PCF. However
if the dmemory is the reason for a stall it is possible for the icache stall to hold the d memory request continuously causing d memory to repeatedly read from memory. This keeps StallF high and
the icache FSM is never allowed to complete.
2021-04-22 10:20:36 -05:00
Ross Thompson
7b3735fc25
Fixed for the instruction spills.
2021-04-21 16:47:05 -05:00
Ross Thompson
532c8771ba
major progress.
...
It's running the icache is imperas tests now.
Compressed does not work yet.
2021-04-21 08:39:54 -05:00
Ross Thompson
f3093ac612
Why was the linter messed up?
...
There are a number of combo loops which need fixing outside the icache. They may be fixed in main.
We get to instruction address 50 now!
2021-04-20 22:06:12 -05:00
Ross Thompson
99424fb983
Progress on icache. Fixed some issues aligning the PC with instruction. Still broken.
2021-04-20 21:19:53 -05:00
Ross Thompson
251ece20fe
Broken icache. Design is done. Time to debug.
2021-04-20 19:55:49 -05:00
Jarred Allen
850f728cc7
Merge branch 'main' into cache
2021-04-19 00:05:23 -04:00
Katherine Parry
d12eb0f4eb
fixed synth bugs in fpu
2021-04-19 00:39:16 +00:00
Noah Boorstin
2af4e2f4ac
slowly more buildroot progress
2021-04-18 18:18:07 -04:00
Noah Boorstin
9bb1233433
neat verilog thing
2021-04-18 17:48:51 -04:00
Noah Boorstin
6954e6df4c
buildroot: sim is now running!
...
yes it only gets through 5 instructions right now. Yes that's my fault.
2021-04-17 14:44:32 -04:00
Noah Boorstin
4f97e9e761
start to add buildroot testbench
...
This still uses testbench-busybear.sv
I think it might be time to finally rename nearly 'busybear' thing to 'linux'
2021-04-16 23:27:29 -04:00
Jarred Allen
aef57cab50
dcache lints
2021-04-15 21:13:56 -04:00
Jarred Allen
7854d838c7
Enable linting of blocks not yet in the hierarchy
2021-04-15 21:13:40 -04:00
bbracker
290b3424e5
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-04-15 21:09:27 -04:00
bbracker
368c94d4ff
working GPIO interrupt demo
2021-04-15 21:09:15 -04:00
Domenico Ottolia
9f13ee3f31
Add tests for scause and ucause
2021-04-15 19:41:25 -04:00
Domenico Ottolia
92bb38fa8c
Add support for vectored interrupts
2021-04-15 19:13:42 -04:00
Domenico Ottolia
eb9e1843fc
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2021-04-15 16:57:27 -04:00
Domenico Ottolia
531423d7e1
Add 32 bit privileged tests
2021-04-15 16:55:39 -04:00
Teo Ene
2814579f30
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2021-04-15 15:29:09 -05:00
Teo Ene
374a93dae6
Quick fix to ahblite missing default statement done in class :)
2021-04-15 15:29:04 -05:00
Thomas Fleming
e780694ee0
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
...
Conflicts:
wally-pipelined/src/mmu/priority_encoder.sv
2021-04-15 16:20:43 -04:00
Thomas Fleming
6dd7591ceb
Change priority encoder to avoid extra assignment
2021-04-15 16:17:35 -04:00
Thomas Fleming
ff9f1e5e72
Connect tlb and icache properly
2021-04-15 14:48:39 -04:00
Teo Ene
ad86295fcf
Temporary change to mmu/priority_encoder.sv
...
Necessary to get synth working
Original HDL is still there, just commented out
2021-04-15 13:37:12 -05:00
Katherine Parry
636e2de9df
integraded the FMA into the FPU
2021-04-15 18:28:00 +00:00
Jarred Allen
81c02bda55
Merge branch 'main' into cache
2021-04-15 13:47:19 -04:00
Ross Thompson
87b716170c
Merge branch 'bpfixes' into main
2021-04-15 09:06:21 -05:00
Shreya Sanghai
0369fc5d1e
Cherry Pick merge of Shreya's localhistory predictor changes into main.
...
fixed minor bugs in localHistory
2021-04-15 09:04:36 -05:00
ShreyaSanghai
6d4042e479
added localHistoryPredictor
2021-04-15 08:58:22 -05:00
Shreya Sanghai
7e9a0602ea
fixed bugs in global history to read latest GHRE
...
Cherry pick Shreya's commits into main branch.
2021-04-15 08:55:22 -05:00
bbracker
e69cc0d23a
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-04-15 09:06:03 -04:00
bbracker
51cdff3e9b
csri lint improvement
2021-04-15 09:05:53 -04:00
Jarred Allen
3717699ad9
Add a comment to explain a detail
2021-04-14 23:14:59 -04:00
Thomas Fleming
3c49fd08f6
Remove imem from testbenches
2021-04-14 20:20:34 -04:00
Jarred Allen
892dfd5a9b
More icache bugfixes
2021-04-14 19:03:33 -04:00
Jarred Allen
c1e2e58ebe
Merge branch 'main' into cache
...
Conflicts:
wally-pipelined/src/cache/dmapped.sv
wally-pipelined/src/cache/line.sv
wally-pipelined/src/ifu/icache.sv
2021-04-14 18:24:32 -04:00
bbracker
8f7ddcfdff
rv64 interrupt servicing
2021-04-14 10:19:42 -04:00
Noah Boorstin
d66fcbc4ab
busybear: use (slightly) less terrible verilog
2021-04-14 00:18:44 -04:00
Noah Boorstin
c75455cc41
busybear testbench updates
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start speculative checking on CSR* satp, *
add some slight delays in some CSR checkings to make them deterministic
I realize this verilog is incredibly un-idiomatic. But I still don't
know of anything better. If you figure it out, please let me know
2021-04-14 00:00:27 -04:00
Thomas Fleming
7d2d6823f1
Fix mmu lint errors
2021-04-13 19:19:58 -04:00
Thomas Fleming
0a9b208729
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2021-04-13 17:15:10 -04:00
Katherine Parry
ef011496a7
Various bugs fixed in FMA
2021-04-13 18:27:13 +00:00
Thomas Fleming
09c9c49541
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
...
Conflicts:
wally-pipelined/src/ebu/pagetablewalker.sv
2021-04-13 13:42:03 -04:00
Thomas Fleming
6188f10732
Move InstrPageFault to fetch stage
2021-04-13 13:39:22 -04:00
Thomas Fleming
dc8a165806
Add lru algorithm to TLB
2021-04-13 13:37:24 -04:00
Teo Ene
1018a10625
Various code syntax changes to bring HDL to a synthesizable level
2021-04-13 11:27:12 -05:00
Jarred Allen
4ae1df1290
Merge branch 'main' into cache
2021-04-13 01:10:03 -04:00
Jarred Allen
fc8b8ad7aa
A few more cache fixes
2021-04-13 01:07:40 -04:00
