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1377 Commits

Author SHA1 Message Date
David Harris
4038c4faa9 ZMerge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-09-14 09:42:17 -07:00
Ross Thompson
2ae62c2869 pipelining of fetch into evict AHB requests. 2022-09-13 17:51:55 -05:00
Ross Thompson
40e7d2648f Renamed signals in the LSU. 2022-09-13 11:47:39 -05:00
David Harris
2babf1fd7a Removed unused signals 2022-09-12 11:35:35 -07:00
David Harris
f45bb25618 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-09-08 16:05:58 -07:00
David Harris
1688d544b9 Moved C to shift before rather than after using in an iteration 2022-09-08 16:05:53 -07:00
David Harris
1c3064af08 divsqrt comment cleanup 2022-09-08 15:40:42 -07:00
Ross Thompson
33ef158ff4 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-09-08 17:15:46 -05:00
David Harris
e0a9b19008 CSA-based completion detection 2022-09-08 14:58:08 -07:00
Ross Thompson
8618045bf2 Optimization. Able to remove hptw address muxes from the E stage. 2022-09-08 15:51:18 -05:00
Ross Thompson
d12ceb46b0 Oups the ahbinterface.sv was accidentally named abhinterface.sv. 2022-09-08 13:21:37 -05:00
Ross Thompson
fbea27bd69 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-09-07 16:36:51 -05:00
Ross Thompson
ae4a55471d Oups fixed order of ending swap with mux between cache and fetch buffer. 2022-09-07 16:29:47 -05:00
David Harris
f628622ea0 Factored out aplusbeq0 unit 2022-09-07 11:36:35 -07:00
David Harris
c2f81e309b Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-09-07 11:11:39 -07:00
David Harris
b0cf73d19c Running 16-bit square root cases first in testfloat 2022-09-07 11:11:35 -07:00
Ross Thompson
fd4b382ec6 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-09-07 12:26:50 -05:00
David Harris
e01b03e9b2 Run 16-bit fsqrt tests first 2022-09-07 10:26:09 -07:00
Ross Thompson
54c55b57cb Named change for ahb tests to be less annoying. 2022-09-07 12:24:41 -05:00
David Harris
d91b4de348 Preprocessing cleanup 2022-09-07 10:21:27 -07:00
Ross Thompson
6581490f9c Modified regression tests to add some ahb configurations. 2022-09-07 12:03:58 -05:00
David Harris
29f015810b Added rv32i config for regression of wally32periph 2022-09-07 09:37:59 -07:00
Ross Thompson
d07c44bcf6 Merge branch 'multimanager' into main 2022-09-07 10:54:27 -05:00
David Harris
29f41c6792 Continued simplifying fdivsqrt postprocessing 2022-09-07 07:02:22 -07:00
David Harris
461b9d370d Continued simplifying fdivsqrt postprocessing 2022-09-07 07:00:13 -07:00
David Harris
825d3169d9 Moving postprocessing into postproc block 2022-09-07 06:42:37 -07:00
David Harris
f40c6b0ec4 fdivsqrtfsm cleanup 2022-09-07 06:32:07 -07:00
David Harris
a0abe48ad2 fdivsqrtfsm cleanup 2022-09-07 06:27:01 -07:00
David Harris
8438546d52 Fixed regression for divsqrt radix2 2022-09-07 06:12:23 -07:00
Ross Thompson
6685b0563e James found a bug in synchronizer. Was not actually back to back flip flops. 2022-09-06 15:06:54 -05:00
Ross Thompson
99e3f55637 Added logic to make burst optional. 2022-09-06 09:21:21 -05:00
Ross Thompson
fcf72bb6ba Added generate around the longer latency version of the ram_ahb.sv 2022-09-06 09:21:03 -05:00
Ross Thompson
20842b38b9 Names changes. 2022-09-05 20:49:35 -05:00
Ross Thompson
4e7a52a7a7 Cleaned up hacks to ram. 2022-09-04 14:52:40 -05:00
Ross Thompson
9d5a7281b8 Modified ram_ahb to work with different latencies. 2022-09-04 14:46:15 -05:00
Ross Thompson
7ae58c6654 Progress towards fixing the select HREADY muxing in uncore. 2022-09-04 13:07:49 -05:00
Ross Thompson
26bfaddb25 Disabled AHB burst mode, which discovered a bug. 
Multimanger bug in how back to back requests were arbitrated.
 2022-09-03 22:31:41 -05:00
cturek
e709ad4145 Old changes to old files 2022-09-03 22:09:55 +00:00
Ross Thompson
3e540a3ca3 Possible fix to AHB burst eviction bug. If HREADY went low during a burst seq the next data phase would only last 1 cycle. 2022-09-02 19:58:41 -05:00
Ross Thompson
4115087b30 Renamed state in buscachefsm to match AHB phases. 2022-09-02 17:17:40 -05:00
Ross Thompson
472fb5e888 Renamed states in busfsm to match AHB phases and book names. 2022-09-02 17:12:36 -05:00
Ross Thompson
15a2fbdd33 Possible fix for AHB trailing ~HREADY bug. 2022-09-02 16:58:35 -05:00
Ross Thompson
851ad4417d Merge branch 'multimanager' of github.com:davidharrishmc/riscv-wally into multimanager 2022-09-02 16:31:07 -05:00
Ross Thompson
2aa5886769 Fixed brom1p1r.sv to have fpga preload. 2022-09-02 15:49:50 -05:00
Ross Thompson
722e1a029e Merge branch 'multimanager' of github.com:davidharrishmc/riscv-wally into multimanager 2022-09-02 13:54:48 -05:00
Ross Thompson
559e093ab5 Fixed up FPGA constraints. 
Added back in the fpga boot rom preload.
 2022-09-02 13:54:35 -05:00
David Harris
648a3aae09 Initial radix 4 square root debuggin 2022-09-01 16:57:57 -07:00
Ross Thompson
83c427c5b5 clean up subword write. 2022-09-01 17:55:19 -05:00
David Harris
247ce70348 Fixed lint errors in square root and improved waveforms in testfloat 2022-09-01 15:49:13 -07:00
Ross Thompson
5b4e744972 marked possible improvement to ahb bus fsms. 2022-08-31 23:57:08 -05:00
David Harris
8fad5073cd fdiv debug 2022-08-31 14:26:31 -07:00
Ross Thompson
5c8631fd16 Reduced busfsm to 3 states! 2022-08-31 16:11:59 -05:00
Ross Thompson
1cd7d8dbfe Simplified. 2022-08-31 15:40:56 -05:00
Ross Thompson
2b528dc8be more renaming. 2022-08-31 14:52:06 -05:00
Ross Thompson
ab4c75cbf5 More renaming. 2022-08-31 14:49:08 -05:00
Ross Thompson
6e85f850a4 Moved files. 
Encapsulated ahbinterface.
 2022-08-31 14:45:01 -05:00
Ross Thompson
fcd1465de1 Renamed AHBCachebusdp to abhcacheinterface. 2022-08-31 14:12:19 -05:00
Ross Thompson
d6d1c5d66d Moved files around. 2022-08-31 14:08:06 -05:00
Ross Thompson
6912656aab Merge branch 'multimanager' into main 2022-08-31 13:10:22 -05:00
Ross Thompson
39c2cad9af Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-08-31 13:10:04 -05:00
David Harris
e64f41f199 Checking in radix 4 square root with qsel, fgen, softc, but not working 2022-08-31 10:54:50 -07:00
Ross Thompson
08d0c1cc83 Major cleanup of multimanager. 2022-08-31 12:40:25 -05:00
Ross Thompson
352f7443c2 Cleanup multimanager. 2022-08-31 12:04:44 -05:00
Ross Thompson
d06c64094b Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-08-31 11:38:29 -05:00
Ross Thompson
1e752c1268 cleanup of multimanager. 2022-08-31 11:38:06 -05:00
Ross Thompson
1663f571ed More Cleanup. 2022-08-31 11:21:02 -05:00
Ross Thompson
68e54977fe More cleanup. 2022-08-31 11:12:38 -05:00
Ross Thompson
0b41ed63f1 More simplifications. 2022-08-31 10:45:16 -05:00
Ross Thompson
ddd9c507fe Trade off. Added additional state to bus fsm separating STATE_CACHE_ACCESS into STATE_CACHE_FETCH and STATE_CACHE_EVICT. This allows removing CacheRWDelay. Saves a bit of logic but fsm is more complex. Also the fsm outputs are simplier. 2022-08-31 10:36:30 -05:00
Ross Thompson
6122c03e39 Removed unused old versions of the bus controllers. 2022-08-31 09:51:54 -05:00
Ross Thompson
1c248e5164 Removed old signals. 2022-08-31 09:50:39 -05:00
DTowersM
dedfadbb14 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally 2022-08-31 00:18:04 +00:00
DTowersM
f9cbc9cf8e fixed qrduino keyerror in embench test 2022-08-31 00:17:58 +00:00
Ross Thompson
5b8f888e21 Maybe fixed it? 2022-08-30 18:08:34 -05:00
Ross Thompson
ccb3e9e24e Updates to wave file. 2022-08-30 17:34:36 -05:00
Ross Thompson
96793d15c0 more progress. 2022-08-30 17:32:32 -05:00
Ross Thompson
2d6a6c6e44 Temporary commit. 2022-08-30 15:40:42 -05:00
Ross Thompson
63a824cca1 More progress. 2022-08-30 15:27:19 -05:00
Ross Thompson
a532eb61ba Progress. 2022-08-30 14:17:00 -05:00
David Harris
5956fbdd62 Fixed checking termination in testfloat testbench 2022-08-30 10:55:21 -07:00
Ross Thompson
c8a5d61cbb new cache bus fsm not working but lints. 
Forgot a few files in the last commit.
 2022-08-30 10:58:07 -05:00
Ross Thompson
5eb1fff27d Have a rough working multi manager! 2022-08-29 17:11:27 -05:00
Ross Thompson
4f40bd07c3 Modified rv32e configuration to use a true ahb bus interface in the lsu and ifu. 2022-08-29 17:04:53 -05:00
David Harris
cb54e95285 commented out lines to have divider work again 2022-08-29 13:01:32 -07:00
David Harris
758b177067 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-08-29 12:01:13 -07:00
David Harris
7b0e43bc10 Initial FDIVSQRT simplification working 2022-08-29 12:01:09 -07:00
Ross Thompson
4d7b905806 Part way through the updated bus fsm for direct AHB in lsu/ifu + multi-manager. 2022-08-29 13:01:24 -05:00
Ross Thompson
40cf4a9ea9 Typo. 2022-08-29 11:40:35 -05:00
Ross Thompson
1c9aed2e7e Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-08-29 11:38:37 -05:00
Ross Thompson
9a7c7e8398 Added comments about planned changes. 2022-08-29 09:48:00 -05:00
David Harris
16cde5f87e Simplify FSM 2022-08-29 04:32:27 -07:00
David Harris
6961e499dc Renamed special case 2022-08-29 04:29:58 -07:00
David Harris
81ec1ac858 Separated out radix 2 and radix 4 stages into different modules 2022-08-29 04:26:14 -07:00
David Harris
b4cb9a678a renamed srt to fdivsqrt 2022-08-29 04:04:05 -07:00
Ross Thompson
35d0b759d1 Removed ignore request from busfsm. 2022-08-28 21:12:27 -05:00
Ross Thompson
dd00474956 Created two new pma regions for dtim and irom. 2022-08-28 13:50:50 -05:00
Ross Thompson
e3e1f29428 Reordered the adrdecs. 2022-08-28 13:38:57 -05:00
Ross Thompson
99e0e5c817 Possible fix. 2022-08-28 13:10:47 -05:00
Ross Thompson
5e77b1bd2b Partial fix to bus + dtim. 2022-08-27 23:44:17 -05:00
David Harris
35d0a951d2 Preliminary work to make DTIM and Bus compatible. Not yet working because accesses to bus are causing illegal address faults on the bus. 2022-08-27 20:31:09 -07:00