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ddd9c507fe
cvw
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pipelined
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Ross Thompson
ddd9c507fe
Trade off. Added additional state to bus fsm separating STATE_CACHE_ACCESS into STATE_CACHE_FETCH and STATE_CACHE_EVICT. This allows removing CacheRWDelay. Saves a bit of logic but fsm is more complex. Also the fsm outputs are simplier.
2022-08-31 10:36:30 -05:00
..
config
fixed wally-config
2022-08-26 22:13:10 -07:00
misc
regression
Maybe fixed it?
2022-08-30 18:08:34 -05:00
src
Trade off. Added additional state to bus fsm separating STATE_CACHE_ACCESS into STATE_CACHE_FETCH and STATE_CACHE_EVICT. This allows removing CacheRWDelay. Saves a bit of logic but fsm is more complex. Also the fsm outputs are simplier.
2022-08-31 10:36:30 -05:00
srt
divider sizes reworked to match book
2022-07-22 22:02:04 +00:00
testbench
renamed srt to fdivsqrt
2022-08-29 04:04:05 -07:00
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