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118 Commits

Author SHA1 Message Date
Domenico Ottolia
c0f054556c Fix bug with IllegalInstrFaultM not getting correct value 2021-05-03 22:48:03 -04:00
Thomas Fleming
0254ca7bf6 Adjust attributes in PMA checker 2021-05-03 21:58:32 -04:00
Domenico Ottolia
5ab86a690b Fix bug that caused stvec to get the wrong value 2021-05-03 17:54:57 -04:00
Thomas Fleming
eda5a267ee Implement PMP checker and revise PMA checker 2021-05-03 17:37:42 -04:00
Thomas Fleming
cfe64e7c24 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 
Conflicts:
	wally-pipelined/src/ebu/ahblite.sv
 2021-05-03 14:02:19 -04:00
Katherine Parry
db95151d8d fpu imperas tests run 2021-05-01 02:18:01 +00:00
Domenico Ottolia
d03ca20dc9 Make vectored interrupt trap handling work, and add tests for mtvec with vectored interrupts 2021-04-29 20:42:14 -04:00
Thomas Fleming
6e5fc107d9 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-04-29 16:30:00 -04:00
ushakya22
9dfbfd5772 fix to pcm bug 2021-04-29 15:21:08 -04:00
Thomas Fleming
5f2bccd88f Clean up PMA checker and begin PMP checker 2021-04-29 02:20:39 -04:00
Ross Thompson
8e5409af66 Icache integrated! 
Merge branch 'icache-almost-working' into main
 2021-04-26 11:48:58 -05:00
bbracker
ba94fa3436 it says I need to merge in order to pull 2021-04-26 07:46:24 -04:00
bbracker
1cc0dcc83f progress on bus and lrsc 2021-04-26 07:43:16 -04:00
Ross Thompson
6e803b724e Merge branch 'tests' into icache-almost-working 2021-04-25 21:25:36 -05:00
Thomas Fleming
288a6d82ce Fix HSIZE and HBURST signal widths in PMA checker 2021-04-23 20:11:43 -04:00
Thomas Fleming
da76b80991 Write PCM to TVAL registers 2021-04-22 16:17:57 -04:00
Thomas Fleming
8fee3b3872 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-04-22 15:37:19 -04:00
Domenico Ottolia
6b4d2e9634 Fix misa synthesis bug (for real now) 2021-04-22 15:35:20 -04:00
Thomas Fleming
38236e9172 Implement first pass at the PMA checker 2021-04-22 15:34:02 -04:00
Domenico Ottolia
fb8f244dab Fix misa bug 2021-04-22 00:59:07 -04:00
Thomas Fleming
4bae666fa1 Implement virtual memory protection 2021-04-21 19:58:36 -04:00
Domenico Ottolia
bf86a809eb Add tests for sepc register 2021-04-20 23:50:53 -04:00
Domenico Ottolia
0c307d2db1 Fix synthesis warnings for privileged unit (replace 'initial' settings) 2021-04-20 17:57:56 -04:00
Domenico Ottolia
9f13ee3f31 Add tests for scause and ucause 2021-04-15 19:41:25 -04:00
Domenico Ottolia
92bb38fa8c Add support for vectored interrupts 2021-04-15 19:13:42 -04:00
bbracker
51cdff3e9b csri lint improvement 2021-04-15 09:05:53 -04:00
bbracker
8f7ddcfdff rv64 interrupt servicing 2021-04-14 10:19:42 -04:00
Thomas Fleming
09c9c49541 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 
Conflicts:
	wally-pipelined/src/ebu/pagetablewalker.sv
 2021-04-13 13:42:03 -04:00
Thomas Fleming
6188f10732 Move InstrPageFault to fetch stage 2021-04-13 13:39:22 -04:00
Teo Ene
1018a10625 Various code syntax changes to bring HDL to a synthesizable level 2021-04-13 11:27:12 -05:00
Domenico Ottolia
65abe13f4f Cause an Illegal Instruction Exception when attempting to write readonly CSRs 2021-04-08 05:12:54 -04:00
Ross Thompson
c91436d3b7 Merge branch 'icache_bp_bug' into tests 
Not sure this merge is right.
 2021-04-06 21:46:40 -05:00
Thomas Fleming
fdb20ee1cf Implement sfence.vma and fix tlb writing 2021-04-01 15:55:05 -04:00
Ross Thompson
9172e52286 Corrected a number of bugs in the branch predictor. 
Added performance counters to individually track
branches; jumps, jump register, jal, and jalr; return.
jump and jump register are special cases of jal and jalr.
Similarlly return is a special case of jalr.
Also added counters to track if the branch direction was wrong,
btb target wrong, or the ras target was wrong.
Finally added one more counter to track if the BP incorrectly predicts
a non-cfi instruction.
 2021-03-31 11:54:02 -05:00
Ross Thompson
a64a37d702 Merge of main with the new icache and the branch predictor. I believe there is a bug in the icache with unaligned memory access. The second part of the access is incorrectly relying on the PCF being the address of the next two bytes of the instruction. However this is not always the case as the branch predictor can get the wrong target address. The icache needs to generate the +2 address internally. 2021-03-30 23:18:20 -05:00
Thomas Fleming
7126ab7864 Complete basic page table walker 2021-03-30 22:19:27 -04:00
Thomas Fleming
e3900bd0fa Finish finite state machines for page table walker 2021-03-25 02:48:40 -04:00
Thomas Fleming
b5003b093a Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-03-25 02:35:21 -04:00
bbracker
02e924e55a instrfaults not respecting stalls bugfix 2021-03-25 00:16:26 -04:00
bbracker
e98dd420bc future work comment about suspicious-looking verilog in csri.sv 2021-03-25 00:10:44 -04:00
Thomas Fleming
b1d849c822 Add all PMP addr registers 2021-03-24 21:58:33 -04:00
Ross Thompson
a99c0502e5 Fixed bugs with the csr interacting with StallW. StallW is required to pervent updating a csr. Now have a working branch predictor and performance counters to track the number of commited branches and mispredictions. 2021-03-24 15:56:55 -05:00
Shreya Sanghai
1d6a2989ed PC counts branch instructions 2021-03-23 14:25:51 -04:00
Shreya Sanghai
bbe0957df5 Merge branch 'gshare' into main 
Conflicts:
	wally-pipelined/regression/wave.do
 2021-03-18 17:25:48 -04:00
Thomas Fleming
8d484174a7 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-03-18 14:36:42 -04:00
Thomas Fleming
7f7597e667 Connect tlb, pagetablewalker, and memory 2021-03-18 14:35:46 -04:00
Noah Boorstin
bc1a0c6ee7 change ifndef to generate/if 2021-03-18 12:50:19 -04:00
Shreya Sanghai
08e9149e20 made performance counters count branch misprediction 2021-03-16 11:24:17 -04:00
Shreya Sanghai
74f1641c5a Merge branch 'counters' into main 
added a configurable number of performance counters
 2021-03-16 11:01:30 -04:00
Thomas Fleming
be6ee84d87 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-03-05 15:46:51 -05:00
Thomas Fleming
7e11317a2d Export SATP_REGW from csrs to MMU modules 2021-03-05 01:22:53 -05:00
Noah Boorstin
f48af209c4 busybear: make CSRs only weird for us 2021-03-05 00:46:32 +00:00
Shreya Sanghai
246dbd05e7 fixed bugs 2021-03-04 12:59:45 -05:00
Shreya Sanghai
f0ec365117 added performance counters 2021-03-04 11:42:52 -05:00
Noah Boorstin
bcc0010498 Merge branch 'main' into busybear 2021-02-28 20:45:08 +00:00
Noah Boorstin
a03796a519 busybear: change sstatus, mstatus reset value 2021-02-28 16:19:03 +00:00
David Harris
cf03afa880 Eliminated flushing pipeline on CSR reads 2021-02-26 17:00:07 -05:00
David Harris
015b632eb1 Cleaned out unused signals 2021-02-26 09:17:36 -05:00
kaveh pezeshki
c7863d58cd merged with main to integrate with AHB 2021-02-26 05:37:10 -08:00
David Harris
c52a99ce2d Fixed fetch stall after jump in bus unit 2021-02-23 09:08:57 -05:00
Noah Boorstin
5835641c6c busybear testbench: check (almost) all the CSRs 2021-02-16 20:03:24 -05:00
David Harris
37dba8fd26 More memory interface, ALU testgen 2021-02-15 10:10:50 -05:00
Noah Boorstin
14cde0d59c Change CSR reset and available bits to conform to OVPsim 
Now actually keeping perfectly in line with OVP for the first 100k instrs. Yay.
 2021-02-04 22:03:45 +00:00
David Harris
a44c2abb12 Minor tweaks 2021-02-02 19:44:37 -05:00
David Harris
d56d7a75a6 Rename ifu/dmem/ebu signals to match uarch diagram 2021-02-02 15:09:24 -05:00
David Harris
aad1d3d7dd Moved writeback pipeline registers from datapth into DMEM and CSR 2021-02-02 13:02:31 -05:00
David Harris
9d7e242596 Moved fpu to temporary location to fix compile and cleaned up interface formatting 2021-02-01 23:44:41 -05:00
David Harris
396cea1ea7 Reorganized src hierarchically 2021-01-30 11:50:37 -05:00