Katherine Parry
ca19b2e215
Fixed writting MStatus FS bits
2021-07-13 13:22:04 -04:00
Katherine Parry
efdec72df1
Fixed writting MStatus FS bits
2021-07-13 13:20:30 -04:00
David Harris
b5dddec858
Fixed InstrValid from W to M stage for CSR performance counters
2021-07-13 13:19:13 -04:00
David Harris
5c2f774c35
Simplified tlbmixer mux to and-or
2021-07-08 23:34:24 -04:00
David Harris
74b6d13195
Fixed missing stall in InstrRet counter
2021-07-08 20:08:04 -04:00
David Harris
032c38b7e7
MMU produces page fault when upper bits aren't equal. Renamed input to MMU to be 'Address' and moved translation mux into MMU out of TLB
2021-07-06 15:29:42 -04:00
Ross Thompson
412691df2d
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2021-07-06 13:45:20 -05:00
Ross Thompson
3345ed7ff4
Merged several of the load/store/instruction access faults inside the mmu.
...
Still need to figure out what is wrong with the generation of load page fault when dtlb hit.
2021-07-06 13:43:53 -05:00
Abe
8854532a79
Disabled MCOUNTINHIBIT to enable csr counters (changed to 32'h0 on line 140)
2021-07-06 12:37:58 -04:00
David Harris
f805aea236
Implemented TSR, TW, TVM, MXR status bits
2021-07-06 01:32:05 -04:00
David Harris
8b23162d6d
Fixed adrdecs to use Access signals for TIMs
2021-07-05 23:42:58 -04:00
David Harris
6bac566bb7
Added support for TVM flag in CSRS and to disabl TLB when MEM_VIRTMEM = 0
2021-07-05 20:35:31 -04:00
David Harris
b23192cf1b
Gave names to for loops in generate blocks for ease of reference
2021-07-04 18:52:16 -04:00
David Harris
7e22ae973e
Fixed MPRV and MXR checks in TLB
2021-07-04 13:20:29 -04:00
David Harris
67e191c6f3
Added support for PMP lock bits in csrm and repartitioned design to pass around 8-bit PMPCFG entries
2021-07-04 11:39:59 -04:00
David Harris
0bd18ff662
Fixed PMPCFG read faults
2021-07-02 17:08:13 -04:00
David Harris
c85e0df1ff
Optimized PMP checker logic and added support for configurable number of PMP registers
2021-07-02 11:04:13 -04:00
bbracker
2155a4e485
Revert "fixed forwarding"
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This reverts commit 86e369df52
2021-06-24 17:39:37 -04:00
bbracker
86e369df52
fixed forwarding
2021-06-24 11:20:21 -04:00
David Harris
1ec90a5e1f
Reversed [0:...] with [...:0] in bus widths across the project
2021-06-21 01:17:08 -04:00
David Harris
d2ec04564b
Cleaned up fcsr code and added _SUPPORTED to optionally disable peripherals
2021-06-20 22:59:04 -04:00
bbracker
23f479d225
remove OVP_CSR_CONFIG because it is an alias of BUSYBEAR
2021-06-20 22:38:25 -04:00
bbracker
83a0a37f8e
make xCOUNTEREN what buildroot expects it to be
2021-06-20 09:22:31 -04:00
David Harris
336936cc39
Cleaned up name of MTIME register in CSRC
2021-06-18 07:53:49 -04:00
bbracker
2bee4eabab
added MTIME and MTIMECMP as read-only CSRs; this likely is not the final version
2021-06-17 12:09:10 -04:00
bbracker
b65adbea63
enable TIME CSR for 32 bit mode as well
2021-06-17 11:34:16 -04:00
bbracker
5a661a7392
provide time and timeh CSRs based on CLINT's counter
2021-06-17 08:38:30 -04:00
bbracker
9bc5ddf5f2
PMPADDRreg size bugfix; PMPADDR_ARRAY_REGW[15] is now useable
2021-06-17 05:19:36 -04:00
bbracker
7b98e7aa2f
mcause test fixes and s-mode interrupt bugfix
2021-06-16 17:37:08 -04:00
David Harris
49b5fa3994
Reverted MIDELEG and MEDELEG to XLEN so busybear passes
2021-06-10 23:47:32 -04:00
David Harris
e41a87be23
Restored counter events
2021-06-10 11:18:58 -04:00
David Harris
3e8026dc21
Configurable number of performance counters
2021-06-10 09:41:26 -04:00
David Harris
01d6ca1e2a
Fixed lint WIDTH errors
2021-06-09 20:58:20 -04:00
David Harris
90e5781471
Start to parameterize number of PMP Entries
2021-06-08 15:29:22 -04:00
bbracker
cc91c774a6
Ah big ole merge! Passes sim-wally-batch and linting, so should be fine
2021-06-08 12:41:25 -04:00
bbracker
e7e4105931
* GPIO comprehensive testing
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* MEPC more aware if M stage has actually committed
* UART interrupt testing progress
* UART added read IIR side effect of lowering THRE intr
2021-06-08 12:32:46 -04:00
David Harris
ff62000e2c
Second attept to commit refactoring config files
2021-06-07 12:37:46 -04:00
Kip Macsai-Goren
49200bd922
Cleaned up some unused signals
2021-06-04 21:04:19 -04:00
Kip Macsai-Goren
22e8e06ac7
moved privilege dfinitions into wally-constants, upgraded relevant includes
2021-06-04 17:55:07 -04:00
Kip Macsai-Goren
1ae529c450
restructured so that pma/pmp are a part of mmu
2021-06-04 17:05:07 -04:00
David Harris
a26bf37be8
Started MMU
2021-06-04 11:59:14 -04:00
bbracker
2c77a13c08
fixed InstrValid signals and implemented less costly MEPC loading
2021-06-02 10:03:19 -04:00
bbracker
39ae743543
turns out I should not have tried renaming FStallD to FPUStallD because that name was already used! All the same it does feel weird to have two such signals floating around \(ah pun!\)
2021-05-28 23:11:37 -04:00
Katherine Parry
06af239e6c
FMV.D.X imperas test passes
2021-05-20 22:17:59 -04:00
Katherine Parry
9464c9022d
floating point infinite loop removed from imperas tests
2021-05-18 10:42:51 -04:00
Thomas Fleming
e27bc1cbf7
Clean up MMU code
2021-05-14 07:12:32 -04:00
Thomas Fleming
19ac77d3fa
Fix compiler warning in PMP checker
2021-05-04 15:18:08 -04:00
Thomas Fleming
3a3c88f5b1
Fix bug in PMP checker
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Now we only enforce PMP regions if at least one is non-null
2021-05-04 03:14:07 -04:00
Thomas Fleming
c9e5af30fa
Disable PMP checker to fix test loops
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There is a bug in the PMP checker where S or U mode attempts to make a
memory access while no PMP registers are set. We currently treat this as
a failure, when this should instead be allowed.
2021-05-04 01:56:05 -04:00
Thomas Fleming
ad40464557
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2021-05-03 23:15:39 -04:00
