Ross Thompson
6bab454b17
Works until pma checker breaks the simulation by reading HADDR rather than data physical address.
2021-06-24 14:42:59 -05:00
Ross Thompson
aeeaf6d919
Progress.
2021-06-24 13:05:22 -05:00
Ross Thompson
9b8bcb8e57
Split the ReadDataW bus into two parts in preparation for the data cache. On the AHB side it is now HRDATAW and on the CPU to data cache side it is ReadDataW. lsu.sv now handles the connection between the two.
...
Also reorganized the inputs and outputs of lsu and pagetablewalker into connects between CPU, pagetablewalker, and AHB.
Finally add DisableTranslation to TLB as teh pagetablewalker will need to force no translation when active regardless of the state of SATP.
With Kip.
2021-06-23 16:43:22 -05:00
Ross Thompson
f74ecbb81e
Updated icache to abhlite to use pa_bits length and moved F/D stage instr register to ifu from icache.
2021-06-23 15:13:56 -05:00
David Harris
580ac1c4df
Made MemPAdrM and related signals PA_BITS wide
2021-06-18 09:36:22 -04:00
bbracker
cc91c774a6
Ah big ole merge! Passes sim-wally-batch and linting, so should be fine
2021-06-08 12:41:25 -04:00
bbracker
e7e4105931
* GPIO comprehensive testing
...
* MEPC more aware if M stage has actually committed
* UART interrupt testing progress
* UART added read IIR side effect of lowering THRE intr
2021-06-08 12:32:46 -04:00
Kip Macsai-Goren
1ae529c450
restructured so that pma/pmp are a part of mmu
2021-06-04 17:05:07 -04:00
Thomas Fleming
e27bc1cbf7
Clean up MMU code
2021-05-14 07:12:32 -04:00
bbracker
8a7fc959eb
small synthesis fixes
2021-05-04 15:21:01 -04:00
Thomas Fleming
8dce32fd22
Remove remnants of InstrReadC
2021-05-03 17:36:25 -04:00
Thomas Fleming
cfe64e7c24
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
...
Conflicts:
wally-pipelined/src/ebu/ahblite.sv
2021-05-03 14:02:19 -04:00
bbracker
182bfdbb0e
rv32 plic test and lint fixes
2021-04-30 06:26:31 -04:00
Thomas Fleming
5f2bccd88f
Clean up PMA checker and begin PMP checker
2021-04-29 02:20:39 -04:00
bbracker
1cc0dcc83f
progress on bus and lrsc
2021-04-26 07:43:16 -04:00
Ross Thompson
27ef10df07
almost working icache.
2021-04-23 16:47:23 -05:00
Ross Thompson
020fb65adf
Fixed icache for 32 bit.
...
Merge branch 'cache' into main
2021-04-22 16:45:29 -05:00
Ross Thompson
c42399bdb5
Yes. The hack to not repeat the d memory operation fixed this issue.
2021-04-22 15:22:56 -05:00
Thomas Fleming
00ce24e67c
Prepare to squash bad ahb accesses
2021-04-22 15:36:45 -04:00
Thomas Fleming
ef80176e2c
Extend stall on leaf page lookups
2021-04-22 01:51:38 -04:00
Thomas Fleming
4bae666fa1
Implement virtual memory protection
2021-04-21 19:58:36 -04:00
Jarred Allen
850f728cc7
Merge branch 'main' into cache
2021-04-19 00:05:23 -04:00
Noah Boorstin
9bb1233433
neat verilog thing
2021-04-18 17:48:51 -04:00
bbracker
368c94d4ff
working GPIO interrupt demo
2021-04-15 21:09:15 -04:00
Jarred Allen
d99b8f772e
Merge from branch 'main'
2021-04-08 17:19:34 -04:00
Thomas Fleming
1cbdaf1f05
Fix extraneous page fault stall
2021-04-03 21:28:24 -04:00
Thomas Fleming
7126ab7864
Complete basic page table walker
2021-03-30 22:19:27 -04:00
Jarred Allen
3b4f0141f4
Begin work on compressed instructions
2021-03-25 14:43:10 -04:00
Jarred Allen
ce6f102fc5
Clean up some stuff
2021-03-25 13:04:54 -04:00
Jarred Allen
602271ff7b
rv64i linear control flow now working
2021-03-25 13:02:26 -04:00
Thomas Fleming
e3900bd0fa
Finish finite state machines for page table walker
2021-03-25 02:48:40 -04:00
bbracker
11d4a8ab34
first pass at PLIC interface
2021-03-22 10:14:21 -04:00
bbracker
85363e941d
AHB bugfixes and sim waveview refactoring
2021-03-18 18:25:12 -04:00
Thomas Fleming
7f7597e667
Connect tlb, pagetablewalker, and memory
2021-03-18 14:35:46 -04:00
David Harris
865c103599
64-bit AMO debugged
2021-03-11 23:18:33 -05:00
Thomas Fleming
1294235837
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
...
Conflicts:
wally-pipelined/src/ebu/ahblite.sv
2021-03-11 00:15:58 -05:00
David Harris
42275e92ed
Initial untested implementation of AMO instructions
2021-03-11 00:11:31 -05:00
Noah Boorstin
2c25e270a2
change flop in ahb controller to use normal flop module
2021-03-10 19:14:02 +00:00
David Harris
9c7da510fb
Created atomic test vector and directories
2021-03-08 09:38:55 -05:00
Thomas Fleming
7e11317a2d
Export SATP_REGW from csrs to MMU modules
2021-03-05 01:22:53 -05:00
Thomas Fleming
394051c02f
Begin hardware page table walker
2021-03-03 17:13:45 -05:00
David Harris
015b632eb1
Cleaned out unused signals
2021-02-26 09:17:36 -05:00
David Harris
b16846bddb
Clean up bus interface code
2021-02-26 01:03:47 -05:00
David Harris
f5e9c91193
All tests passing with bus interface
2021-02-24 07:25:03 -05:00
David Harris
817f81c356
Debugging Bus interface
2021-02-22 13:48:30 -05:00
David Harris
37dba8fd26
More memory interface, ALU testgen
2021-02-15 10:10:50 -05:00
David Harris
183a2dcfb5
Debugging bus interface.
2021-02-10 01:43:54 -05:00
David Harris
2357f5513b
Debugging instruction fetch
2021-02-09 11:02:17 -05:00
David Harris
63c7c18771
Fixed lw by delaying read value by one cycle
2021-02-07 23:28:21 -05:00
David Harris
3551cc859b
Data memory bus integration
2021-02-07 23:21:55 -05:00
