forked from Github_Repos/cvw
9b8bcb8e57
Also reorganized the inputs and outputs of lsu and pagetablewalker into connects between CPU, pagetablewalker, and AHB. Finally add DisableTranslation to TLB as teh pagetablewalker will need to force no translation when active regardless of the state of SATP. With Kip.
236 lines
11 KiB
Systemverilog
236 lines
11 KiB
Systemverilog
///////////////////////////////////////////
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// ahblite.sv
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//
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// Written: David_Harris@hmc.edu 9 January 2021
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// Modified:
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//
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// Purpose: AHB Lite External Bus Unit
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// See ARM_HIH0033A_AMBA_AHB-Lite_SPEC 1.0
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// Arbitrates requests from instruction and data streams
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// Connects hart to peripherals and I/O pins on SOC
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// Bus width presently matches XLEN
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// Anticipate replacing this with an AXI bus interface to communicate with FPGA DRAM/Flash controllers
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//
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// A component of the Wally configurable RISC-V project.
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//
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// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
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//
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// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation
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// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy,
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// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software
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// is furnished to do so, subject to the following conditions:
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//
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// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
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//
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// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
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// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
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// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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///////////////////////////////////////////
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`include "wally-config.vh"
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package ahbliteState;
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typedef enum logic [3:0] {IDLE, MEMREAD, MEMWRITE, INSTRREAD, ATOMICREAD, ATOMICWRITE, MMUTRANSLATE} statetype;
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endpackage
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module ahblite (
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input logic clk, reset,
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input logic StallW, FlushW,
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// Load control
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input logic UnsignedLoadM,
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input logic [1:0] AtomicMaskedM,
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input logic [6:0] Funct7M,
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// Signals from Instruction Cache
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input logic [`PA_BITS-1:0] InstrPAdrF, // *** rename these to match block diagram
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input logic InstrReadF,
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output logic [`XLEN-1:0] InstrRData,
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output logic InstrAckF,
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// Signals from Data Cache
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input logic [`PA_BITS-1:0] MemPAdrM,
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input logic MemReadM, MemWriteM,
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input logic [`XLEN-1:0] WriteDataM,
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input logic [1:0] MemSizeM,
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// Signals from MMU
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input logic MMUStall,
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input logic [`XLEN-1:0] MMUPAdr,
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input logic MMUTranslate,
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output logic [`XLEN-1:0] MMUReadPTE,
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output logic MMUReady,
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// Signals from PMA checker
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input logic DSquashBusAccessM, ISquashBusAccessF,
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// Signals to PMA checker (metadata of proposed access)
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output logic AtomicAccessM, ExecuteAccessF, WriteAccessM, ReadAccessM,
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// Return from bus
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output logic [`XLEN-1:0] HRDATAW,
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// AHB-Lite external signals
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input logic [`AHBW-1:0] HRDATA,
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input logic HREADY, HRESP,
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output logic HCLK, HRESETn,
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output logic [31:0] HADDR,
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output logic [`AHBW-1:0] HWDATA,
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output logic HWRITE,
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output logic [2:0] HSIZE,
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output logic [2:0] HBURST,
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output logic [3:0] HPROT,
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output logic [1:0] HTRANS,
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output logic HMASTLOCK,
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// Delayed signals for writes
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output logic [2:0] HADDRD,
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output logic [3:0] HSIZED,
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output logic HWRITED,
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// Stalls
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output logic /*InstrUpdate, */DataStall,
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output logic CommitM, MemAckW
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);
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logic GrantData;
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logic [31:0] AccessAddress;
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logic [2:0] AccessSize, PTESize, ISize;
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logic [`AHBW-1:0] HRDATAMasked, ReadDataM, CapturedHRDATAMasked, HRDATANext, WriteData;
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logic IReady, DReady;
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logic CaptureDataM,CapturedDataAvailable;
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assign HCLK = clk;
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assign HRESETn = ~reset;
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// *** initially support AHBW = XLEN
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// track bus state
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// Data accesses have priority over instructions. However, if a data access comes
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// while an instruction read is occuring, the instruction read finishes before
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// the data access can take place.
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import ahbliteState::*;
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statetype BusState, ProposedNextBusState, NextBusState;
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flopenl #(.TYPE(statetype)) busreg(HCLK, ~HRESETn, 1'b1, NextBusState, IDLE, BusState);
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// This case statement computes the desired next state for the AHBlite,
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// prioritizing address translations, then atomics, then data accesses, and
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// finally instructions. This proposition controls HADDR so the PMA and PMP
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// checkers can determine whether the access is allowed. If not, the actual
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// NextWalkerState is set to IDLE.
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// *** This ability to squash accesses must be replicated by any bus
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// interface that might be used in place of the ahblite.
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always_comb
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case (BusState)
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IDLE: if (MMUTranslate) ProposedNextBusState = MMUTRANSLATE;
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else if (AtomicMaskedM[1]) ProposedNextBusState = ATOMICREAD;
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else if (MemReadM) ProposedNextBusState = MEMREAD; // Memory has priority over instructions
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else if (MemWriteM) ProposedNextBusState = MEMWRITE;
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else if (InstrReadF) ProposedNextBusState = INSTRREAD;
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else ProposedNextBusState = IDLE;
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MMUTRANSLATE: if (~HREADY) ProposedNextBusState = MMUTRANSLATE;
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else ProposedNextBusState = IDLE;
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ATOMICREAD: if (~HREADY) ProposedNextBusState = ATOMICREAD;
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else ProposedNextBusState = ATOMICWRITE;
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ATOMICWRITE: if (~HREADY) ProposedNextBusState = ATOMICWRITE;
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else if (InstrReadF) ProposedNextBusState = INSTRREAD;
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else ProposedNextBusState = IDLE;
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MEMREAD: if (~HREADY) ProposedNextBusState = MEMREAD;
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else if (InstrReadF) ProposedNextBusState = INSTRREAD;
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else ProposedNextBusState = IDLE;
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MEMWRITE: if (~HREADY) ProposedNextBusState = MEMWRITE;
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else if (InstrReadF) ProposedNextBusState = INSTRREAD;
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else ProposedNextBusState = IDLE;
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INSTRREAD: if (~HREADY) ProposedNextBusState = INSTRREAD;
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else ProposedNextBusState = IDLE; // if (InstrReadF still high)
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default: ProposedNextBusState = IDLE;
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endcase
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// Determine access type (important for determining whether to fault)
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assign AtomicAccessM = (ProposedNextBusState == ATOMICREAD) || (ProposedNextBusState == ATOMICWRITE);
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assign ExecuteAccessF = (ProposedNextBusState == INSTRREAD);
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assign WriteAccessM = (ProposedNextBusState == MEMWRITE) || (ProposedNextBusState == ATOMICWRITE);
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assign ReadAccessM = (ProposedNextBusState == MEMREAD) || (ProposedNextBusState == ATOMICREAD) ||
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(ProposedNextBusState == MMUTRANSLATE);
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// The PMA and PMP checkers can decide to squash the access
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assign NextBusState = (DSquashBusAccessM || ISquashBusAccessF) ? IDLE : ProposedNextBusState;
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// stall signals
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// Note that we need to extend both stalls when MMUTRANSLATE goes to idle,
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// since translation might not be complete.
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assign #2 DataStall = ((NextBusState == MEMREAD) || (NextBusState == MEMWRITE) ||
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(NextBusState == ATOMICREAD) || (NextBusState == ATOMICWRITE) ||
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MMUStall);
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//assign #1 InstrStall = ((NextBusState == INSTRREAD) || (NextBusState == INSTRREADC) ||
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// MMUStall);
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// bus outputs
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assign #1 GrantData = (ProposedNextBusState == MEMREAD) || (ProposedNextBusState == MEMWRITE) ||
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(ProposedNextBusState == ATOMICREAD) || (ProposedNextBusState == ATOMICWRITE);
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assign #1 AccessAddress = (GrantData) ? MemPAdrM[31:0] : InstrPAdrF[31:0];
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assign #1 HADDR = (MMUTranslate) ? MMUPAdr[31:0] : AccessAddress;
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generate
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if (`XLEN == 32) assign PTESize = 3'b010; // in rv32, PTEs are 4 bytes
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else assign PTESize = 3'b011; // in rv64, PTEs are 8 bytes
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endgenerate
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assign ISize = 3'b010; // 32 bit instructions for now; later improve for filling cache with full width; ignored on reads anyway
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assign #1 AccessSize = (GrantData) ? {1'b0, MemSizeM} : ISize;
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assign #1 HSIZE = (MMUTranslate) ? PTESize : AccessSize;
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assign HBURST = 3'b000; // Single burst only supported; consider generalizing for cache fillsfH
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assign HPROT = 4'b0011; // not used; see Section 3.7
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assign HTRANS = (NextBusState != IDLE) ? 2'b10 : 2'b00; // NONSEQ if reading or writing, IDLE otherwise
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assign HMASTLOCK = 0; // no locking supported
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assign HWRITE = (NextBusState == MEMWRITE) || (NextBusState == ATOMICWRITE);
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// delay write data by one cycle for
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flop #(`XLEN) wdreg(HCLK, WriteData, HWDATA); // delay HWDATA by 1 cycle per spec; *** assumes AHBW = XLEN
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// delay signals for subword writes
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flop #(3) adrreg(HCLK, HADDR[2:0], HADDRD);
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flop #(4) sizereg(HCLK, {UnsignedLoadM, HSIZE}, HSIZED);
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flop #(1) writereg(HCLK, HWRITE, HWRITED);
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// Route signals to Instruction and Data Caches
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// *** assumes AHBW = XLEN
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assign MMUReady = (BusState == MMUTRANSLATE && HREADY);
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assign InstrRData = HRDATA;
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assign InstrAckF = (BusState == INSTRREAD) && (NextBusState != INSTRREAD);
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assign CommitM = (BusState == MEMREAD) || (BusState == MEMWRITE) || (BusState == ATOMICREAD) || (BusState == ATOMICWRITE);
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// *** Bracker 6/5/21: why is this W stage?
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assign MemAckW = (BusState == MEMREAD) && (NextBusState != MEMREAD) || (BusState == MEMWRITE) && (NextBusState != MEMWRITE) ||
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((BusState == ATOMICREAD) && (NextBusState != ATOMICREAD)) || ((BusState == ATOMICWRITE) && (NextBusState != ATOMICWRITE));
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assign MMUReadPTE = HRDATA;
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// Carefully decide when to update ReadDataW
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// ReadDataMstored holds the most recent memory read.
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// We need to wait until the pipeline actually advances before we can update the contents of ReadDataW
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// (or else the W stage will accidentally get the M stage's data when the pipeline does advance).
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assign CaptureDataM = ((BusState == MEMREAD) && (NextBusState != MEMREAD)) ||
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((BusState == ATOMICREAD) && (NextBusState != ATOMICREAD));
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flopenr #(`XLEN) ReadDataNewWReg(clk, reset, CaptureDataM, HRDATAMasked, CapturedHRDATAMasked);
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always @(posedge HCLK, negedge HRESETn)
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if (~HRESETn)
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CapturedDataAvailable <= #1 1'b0;
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else
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CapturedDataAvailable <= #1 (StallW) ? (CaptureDataM | CapturedDataAvailable) : 1'b0;
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always_comb
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casez({StallW && (BusState != ATOMICREAD),CapturedDataAvailable})
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2'b00: HRDATANext = HRDATAMasked;
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2'b01: HRDATANext = CapturedHRDATAMasked;
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2'b1?: HRDATANext = HRDATAW;
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endcase
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flopr #(`XLEN) ReadDataOldWReg(clk, reset, HRDATANext, HRDATAW);
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// Extract and sign-extend subwords if necessary
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subwordread swr(.*);
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// Handle AMO instructions if applicable
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generate
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if (`A_SUPPORTED) begin
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logic [`XLEN-1:0] AMOResult;
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// amoalu amoalu(.a(HRDATA), .b(WriteDataM), .funct(Funct7M), .width(MemSizeM),
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// .result(AMOResult));
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amoalu amoalu(.srca(HRDATAW), .srcb(WriteDataM), .funct(Funct7M), .width(MemSizeM),
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.result(AMOResult));
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mux2 #(`XLEN) wdmux(WriteDataM, AMOResult, AtomicMaskedM[1], WriteData);
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end else
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assign WriteData = WriteDataM;
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endgenerate
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endmodule
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