forked from Github_Repos/cvw
149 lines
6.8 KiB
Systemverilog
149 lines
6.8 KiB
Systemverilog
///////////////////////////////////////////
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// ahblite.sv
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//
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// Written: David_Harris@hmc.edu 9 January 2021
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// Modified:
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//
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// Purpose: AHB Lite External Bus Unit
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// See ARM_HIH0033A_AMBA_AHB-Lite_SPEC 1.0
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// Arbitrates requests from instruction and data streams
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// Connects hart to peripherals and I/O pins on SOC
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// Bus width presently matches XLEN
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// Anticipate replacing this with an AXI bus interface to communicate with FPGA DRAM/Flash controllers
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//
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// A component of the Wally configurable RISC-V project.
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//
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// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
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//
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// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation
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// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy,
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// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software
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// is furnished to do so, subject to the following conditions:
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//
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// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
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//
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// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
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// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
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// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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///////////////////////////////////////////
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`include "wally-config.vh"
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module ahblite (
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input logic clk, reset,
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input logic StallW, FlushW,
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// Load control
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input logic UnsignedLoadM,
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// Signals from Instruction Cache
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input logic [`XLEN-1:0] InstrPAdrF, // *** rename these to match block diagram
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input logic InstrReadF,
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output logic [`XLEN-1:0] InstrRData,
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// Signals from Data Cache
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input logic [`XLEN-1:0] MemPAdrM,
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input logic MemReadM, MemWriteM,
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input logic [`XLEN-1:0] WriteDataM,
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input logic [1:0] MemSizeM,
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// Return from bus
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output logic [`XLEN-1:0] ReadDataW,
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// AHB-Lite external signals
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input logic [`AHBW-1:0] HRDATA,
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input logic HREADY, HRESP,
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output logic HCLK, HRESETn,
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output logic [31:0] HADDR,
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output logic [`AHBW-1:0] HWDATA,
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output logic HWRITE,
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output logic [2:0] HSIZE,
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output logic [2:0] HBURST,
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output logic [3:0] HPROT,
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output logic [1:0] HTRANS,
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output logic HMASTLOCK,
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// Delayed signals for writes
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output logic [2:0] HADDRD,
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output logic [3:0] HSIZED,
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output logic HWRITED,
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// Stalls
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output logic InstrStall,/*InstrUpdate, */DataStall
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);
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logic GrantData;
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logic [2:0] ISize;
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logic [`AHBW-1:0] HRDATAMasked, ReadDataM, ReadDataPreW;
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logic IReady, DReady;
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logic CaptureDataM;
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assign HCLK = clk;
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assign HRESETn = ~reset;
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// *** initially support HABW = XLEN
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// track bus state
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// Data accesses have priority over instructions. However, if a data access comes
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// while an instruction read is occuring, the instruction read finishes before
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// the data access can take place.
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typedef enum {IDLE, MEMREAD, MEMWRITE, INSTRREAD, INSTRREADMEMPENDING} statetype;
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statetype BusState, NextBusState;
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flopenl #(.TYPE(statetype)) busreg(HCLK, ~HRESETn, 1'b1, NextBusState, IDLE, BusState);
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always_comb
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case (BusState)
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IDLE: if (MemReadM) NextBusState = MEMREAD; // Memory has pirority over instructions
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else if (MemWriteM) NextBusState = MEMWRITE;
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else if (InstrReadF) NextBusState = INSTRREAD;
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else NextBusState = IDLE;
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MEMREAD: if (~HREADY) NextBusState = MEMREAD;
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else if (InstrReadF) NextBusState = INSTRREAD;
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else NextBusState = IDLE;
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MEMWRITE: if (~HREADY) NextBusState = MEMWRITE;
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else if (InstrReadF) NextBusState = INSTRREAD;
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else NextBusState = IDLE;
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INSTRREAD: //if (~HREADY & (MemReadM | MemWriteM)) NextBusState = INSTRREADMEMPENDING; // *** shouldn't happen, delete
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if (~HREADY) NextBusState = INSTRREAD;
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else NextBusState = IDLE; // if (InstrReadF still high)
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INSTRREADMEMPENDING: if (~HREADY) NextBusState = INSTRREADMEMPENDING; // *** shouldn't happen, delete
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else if (MemReadM) NextBusState = MEMREAD;
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else NextBusState = MEMWRITE; // must be write if not a read. Don't return to idle.
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endcase
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// stall signals
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assign #2 DataStall = (NextBusState == MEMREAD) || (NextBusState == MEMWRITE) || (NextBusState == INSTRREADMEMPENDING);
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assign #1 InstrStall = (NextBusState == INSTRREAD);
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// DH 2/20/22: A cyclic path presently exists
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// HREADY->NextBusState->GrantData->HSIZE->HSELUART->HREADY
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// This is because the peripherals assert HREADY on the same cycle
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// When memory is working, also fix the peripherals to respond on the subsequent cycle
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// and this path should be fixed.
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// bus outputs
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assign #1 GrantData = (NextBusState == MEMREAD) || (NextBusState == MEMWRITE);
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assign #1 HADDR = (GrantData) ? MemPAdrM[31:0] : InstrPAdrF[31:0];
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assign ISize = 3'b010; // 32 bit instructions for now; later improve for filling cache with full width; ignored on reads anyway
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assign #1 HSIZE = GrantData ? {1'b0, MemSizeM} : ISize;
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assign HBURST = 3'b000; // Single burst only supported; consider generalizing for cache fillsfH
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assign HPROT = 4'b0011; // not used; see Section 3.7
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assign HTRANS = (NextBusState != IDLE) ? 2'b10 : 2'b00; // NONSEQ if reading or writing, IDLE otherwise
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assign HMASTLOCK = 0; // no locking supported
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assign HWRITE = (NextBusState == MEMWRITE);
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// delay write data by one cycle for
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flop #(`XLEN) wdreg(HCLK, WriteDataM, HWDATA); // delay HWDATA by 1 cycle per spec; *** assumes AHBW = XLEN
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// delay signals for subword writes
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flop #(3) adrreg(HCLK, HADDR[2:0], HADDRD);
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flop #(4) sizereg(HCLK, {UnsignedLoadM, HSIZE}, HSIZED);
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flop #(1) writereg(HCLK, HWRITE, HWRITED);
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// Route signals to Instruction and Data Caches
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// *** assumes AHBW = XLEN
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assign InstrRData = HRDATA;
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assign ReadDataM = HRDATAMasked; // changed from W to M dh 2/7/2021
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assign CaptureDataM = (BusState == MEMREAD) && (NextBusState != MEMREAD);
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flopenr #(`XLEN) ReadDataPreWReg(clk, reset, CaptureDataM, ReadDataM, ReadDataPreW); // *** this may break when there is no instruction read after data read
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flopenr #(`XLEN) ReadDataWReg(clk, reset, ~StallW, ReadDataPreW, ReadDataW);
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subwordread swr(.*);
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endmodule
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