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ba90d868db
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117 Commits

Author SHA1 Message Date
Cedar Turek
ba90d868db took out broken muxes 2022-12-30 15:13:52 -08:00
Cedar Turek
545a3ff363 various cleanup 2022-12-30 14:31:23 -08:00
Cedar Turek
3170130c94 Code cleanup 2022-12-30 14:13:33 -08:00
Cedar Turek
158e23b5a5 commented complicated step/right shift calc 2022-12-30 12:03:10 -08:00
Cedar Turek
eef1d4dd66 comment cleaning 2022-12-30 11:11:34 -08:00
Cedar Turek
7e5cafeda3 Described internal signals of fdivsqrt top 2022-12-30 11:01:02 -08:00
Cedar Turek
8cb4a7a69a Commented fdivsqrt module 2022-12-30 10:52:25 -08:00
Cedar Turek
3115df9380 Begin commenting divsqrt 2022-12-30 10:43:02 -08:00
David Harris
58218dbdd1 continued simplifying integer division special cases 2022-12-30 07:40:28 -08:00
David Harris
bd16fd79d4 started simplifying integer division special cases 2022-12-30 07:34:26 -08:00
David Harris
30dc45c764 removed duplicate quotient mux 2022-12-30 07:17:38 -08:00
David Harris
61230c967c simplified sign handling mux 2022-12-30 07:10:47 -08:00
David Harris
3c475455d9 Clean up sqrt preproc 2022-12-30 07:00:48 -08:00
David Harris
4fb8396867 Clean up sqrt initialization mux 2022-12-30 06:55:20 -08:00
David Harris
dba3ffe767 Reduced size of preproc right shift 2022-12-30 06:47:40 -08:00
David Harris
0e9bd5dab5 fdivsqrtpreproc shift simplification 2022-12-30 06:45:51 -08:00
David Harris
e9b314f902 fdiv cleanup, reduce number of rv32f fma_b15 tests being run to speed up regression 2022-12-30 06:40:25 -08:00
David Harris
ef37070eee Fixed register timing failure on SpecialCaseM in fdivsqrt 2022-12-29 21:09:23 -08:00
David Harris
776f4714af Clean up names and comments in divsqrt 2022-12-29 08:02:44 -08:00
David Harris
6664cb9db4 Factored out hardware unique to RV64 and to IDIV 2022-12-29 07:36:26 -08:00
David Harris
7780b44973 fdivsqrtfsm conditional on IDIV (fixed typo) 2022-12-27 22:16:48 -08:00
David Harris
5ee44b7405 fdivsqrtfsm conditional on IDIV 2022-12-27 22:15:45 -08:00
David Harris
db933aa7e2 fdivsqrtfsm conditional on IDIV 2022-12-27 22:14:09 -08:00
Cedar Turek
ef360f0539 idiv passing radix 2, four copies 2022-12-27 22:11:18 -08:00
David Harris
9964fc9ebe Moved IDIV in fdivsqrtfms into generate block 2022-12-27 22:04:50 -08:00
David Harris
a832605658 Moved IDIV for postproc into generate block 2022-12-27 22:02:14 -08:00
David Harris
d59878a886 Moved IDIV_ON_FP into conditional block in fdivsqrtpreproc 2022-12-27 21:53:00 -08:00
Cedar Turek
a559abe554 Fixed cycles for multiple iterations. 2-copies radix 2 passing regression. 2022-12-27 21:34:27 -08:00
David Harris
c08811357c Renamed muldiv to mdu 2022-12-27 19:57:10 -08:00
David Harris
dfc0b5d1ad Removed MDUE from unnecessary places in fdivsqrt 2022-12-27 10:42:40 -08:00
David Harris
4850d058b2 fdiv typo 2022-12-27 10:30:42 -08:00
David Harris
acc9498ae2 Made SqrtE only true on square root so gating with ~MDUE can be removed) 2022-12-27 10:27:07 -08:00
David Harris
e34b8139af Check for non-negative W in int sign handling 2022-12-27 06:35:17 -08:00
Cedar Turek
f48b7d7ef9 fpu idiv working on all configs with 1 copy of radix 2! 2022-12-26 23:18:28 -08:00
Cedar Turek
0b14aa852d fpu passing idiv tests on rv32gc 1 copy of radix 2! 2022-12-26 21:47:56 -08:00
Cedar Turek
bebaf08bed took out otfc swap. updated postprocessing quotient/remainder logic for int div. 2022-12-26 21:03:56 -08:00
David Harris
c326a274ac Fixed early termination for square root 2022-12-26 08:54:57 -08:00
David Harris
2de66e9eef Moved fdivsqrtexpcalc to its own file 2022-12-26 08:45:43 -08:00
cturek
cc6f219bdd Added A Sign register. Fixed postprocessing logic for postinc and rem calculation. 2022-12-24 06:46:52 +00:00
David Harris
f038494760 Commented out fdiv early termination - broke fsqrt test 2022-12-23 00:58:55 -08:00
David Harris
e061bacc9d Fixed early termination on fdivsqrt 2022-12-23 00:53:55 -08:00
David Harris
9e21358d75 Removed unused signals from FPU 2022-12-23 00:18:39 -08:00
David Harris
0a7ed944a5 Revert to 98b824 2022-12-22 23:58:14 -08:00
David Harris
56312cd0a6 Clean up unused FPU signals 2022-12-22 23:53:09 -08:00
David Harris
4d509f94ec FDIV merge 2022-12-22 23:03:03 -08:00
David Harris
2d72bed1f4 Removed unused signals in FPU and CSR 2022-12-22 22:59:05 -08:00
cturek
ccbad67497 Added negative-result int diviison support in U and UM registers. 13 tests pass! 2022-12-22 16:25:37 +00:00
cturek
1b7ed72ece Moved swap from qslc to otfc 2022-12-22 15:44:50 +00:00
cturek
80ca75e216 Added ForwardedSrcAM to postprocessor. Now passing 8 tests on rv32gc. 2022-12-22 05:44:55 +00:00
cturek
0b4d81bd4a worked out some bugs with int div cycles 2022-12-22 02:22:01 +00:00