117 Commits

Author	SHA1	Message	Date
amaiuolo	000117fcd4	added amaiuolo@hmc.edu	2022-10-13 22:36:52 +00:00
David Harris	6092ca757a	New fdivsqrtqsel4cmp module based on comparators rather than table lookup	2022-10-09 04:47:44 -07:00
David Harris	dceb6f9034	Moved shift into divsqrt stage and cleaned up comments	2022-10-09 04:45:45 -07:00
David Harris	55e4911cf0	fdivsqrt code cleanup	2022-10-09 03:37:27 -07:00
David Harris	fc4146f409	Adding start signals for integer divider to fdivsqrt	2022-09-29 16:30:25 -07:00
cturek	c72e2e5d49	Added integer inputs and flags to divsqrt	2022-09-29 23:08:27 +00:00
David Harris	cfa83fdd98	For radix 4 division, fixed initial C and then could remove unexplained shift from divshiftcalc	2022-09-21 13:30:35 -07:00
David Harris	f87e15388a	commented SpecialCase	2022-09-21 05:02:08 -07:00
David Harris	b21e36a788	Added SpecialCaseReg to hold SpecialCase for fdivsqrtpostproc	2022-09-21 04:55:43 -07:00
David Harris	437fd52bf6	Gated sticky bit in fdiv with SpecialCase	2022-09-20 20:05:00 -07:00
David Harris	9c8edb9cb6	renamed u to udigit to avoid conflict with U	2022-09-20 19:29:23 -07:00
cturek	49a1259cf9	Fixed fgen4	2022-09-20 20:00:01 +00:00
David Harris	811f498f63	renamed q to u for unified digit selection	2022-09-20 04:35:14 -07:00
David Harris	705a2bd97b	Removed D2 and D2b from radix2 stage	2022-09-20 04:20:38 -07:00
David Harris	c77ec2aa9c	Simplified UM initialization	2022-09-20 04:18:12 -07:00
David Harris	956011b40b	fdivsqrtfgen4 comments	2022-09-20 04:13:21 -07:00
David Harris	8d1408a9d6	Moved fpu modules into subdirectories	2022-09-20 04:12:05 -07:00