Ross Thompson
dd00474956
Created two new pma regions for dtim and irom.
2022-08-28 13:50:50 -05:00
Ross Thompson
99e0e5c817
Possible fix.
2022-08-28 13:10:47 -05:00
Ross Thompson
5e77b1bd2b
Partial fix to bus + dtim.
2022-08-27 23:44:17 -05:00
David Harris
35d0a951d2
Preliminary work to make DTIM and Bus compatible. Not yet working because accesses to bus are causing illegal address faults on the bus.
2022-08-27 20:31:09 -07:00
David Harris
3959902c5b
Adding decoding for dtim. Added rv32ic_wally32periph test, which should hang until decoder overrides bus
2022-08-27 05:31:56 -07:00
David Harris
921a49921b
Set correct size of IROM/DTIM and allow FLEN>XLEN with DTIM
2022-08-26 21:05:20 -07:00
David Harris
6409548c8b
Replaced DTIM and IROM with DTIM_SUPPORTED, IROM_SUPPORTED, and base and range for each
2022-08-26 20:26:12 -07:00
David Harris
906f6f2990
Renamed DMEM to DTIM and added checks about compatibility of DTIM/IROM and virtmem
2022-08-26 20:12:03 -07:00
David Harris
841eae58ca
Fixed endian swapping on bus only
2022-08-26 19:58:04 -07:00
David Harris
af2e71046e
Fixed rv32e LSU and IFU issues
2022-08-25 20:02:38 -07:00
David Harris
8cbdbb1c38
lsu simplification
2022-08-25 18:52:42 -07:00
David Harris
d507bb3d70
busfsm simplified
2022-08-25 18:36:53 -07:00
David Harris
dc52f55aa6
Removed unused signals
2022-08-25 18:34:39 -07:00
David Harris
50826c0b61
Removed unused signals
2022-08-25 18:30:46 -07:00
David Harris
7cbca2dd22
Removed UncachedBusRead and UncachedBusWrite
2022-08-25 18:24:39 -07:00
David Harris
845807a329
Restored ahbtranstype
2022-08-25 18:22:26 -07:00
David Harris
4ab678ed48
Removed ahbtranstype
2022-08-25 18:21:45 -07:00
David Harris
f405a191af
Removed WordCountFlag
2022-08-25 18:21:18 -07:00
David Harris
db7698202d
Removed UncachedAccess
2022-08-25 18:20:52 -07:00
David Harris
7801ed48b3
Removed UncachedRW
2022-08-25 18:19:41 -07:00
David Harris
bb4ae908db
Removed CacheBusAck
2022-08-25 18:17:34 -07:00
David Harris
85b5587678
Removed SelUncachedAdr
2022-08-25 18:15:59 -07:00
David Harris
555083b0c3
Removed Cache_Enabled
2022-08-25 18:13:34 -07:00
David Harris
b982db5bd5
Removed STATE_BUS_FETCH and STATE_BUS_WRITE
2022-08-25 18:12:09 -07:00
David Harris
de9ec7cc2e
Removed CacheFetchLine and CacheWriteLine
2022-08-25 18:10:15 -07:00
David Harris
fb5ddc476c
Removed CountEn
2022-08-25 18:05:44 -07:00
David Harris
7eae6765df
Removed wordcount
2022-08-25 18:04:49 -07:00
David Harris
73419f0d41
Added buscachefsm for system with bus and cache
2022-08-25 18:01:01 -07:00
David Harris
0b918d6916
Separated busdp for cache from simpler logic for no cache
2022-08-25 17:54:04 -07:00
David Harris
5c1934208a
Simplified swbytemask
2022-08-25 17:32:16 -07:00
David Harris
352bf88ac0
FIxed wallypipelinedsoc merge conflict
2022-08-25 15:36:47 -07:00
David Harris
b96942e84c
Removed delayed AHB signals from top level
2022-08-25 15:34:14 -07:00
Ross Thompson
ad3e632119
Almost fixed issues with irom and dtim address selection.
2022-08-25 15:52:25 -05:00
Ross Thompson
bbf668e460
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-08-25 14:45:02 -05:00
David Harris
5b3c68fe74
ahblite cleanup
2022-08-25 12:44:25 -07:00
Ross Thompson
502eb0f5d1
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-08-25 14:40:52 -05:00
David Harris
d7be94fab2
Cleaned up SelBusWord
2022-08-25 11:18:13 -07:00
David Harris
7a129af9ad
Removed M sufix from busdp signals
2022-08-25 11:13:01 -07:00
David Harris
84ba62a04c
Renamed LSUFunct3M to Funct3 in busdp
2022-08-25 11:08:12 -07:00
David Harris
78618f5fc0
Renaming LSU signals from busdp
2022-08-25 11:05:10 -07:00
David Harris
cd02c894df
renamed BusBuffer to FetchBuffer
2022-08-25 10:44:39 -07:00
David Harris
5dc4fb757a
Continued busdp/ebu simplification
2022-08-25 10:20:02 -07:00
David Harris
89860588b8
Renamed AHB signals coming out of LSU to LSH_<AHBNAME>
2022-08-25 09:52:08 -07:00
Ross Thompson
bd9401179d
BROKEN. Don't use this commit.
...
Issue running cacheless with bus.
2022-08-25 11:02:46 -05:00
David Harris
4ecdbb308a
Renamed DCache to Cache in busdp/busfsm signal interface
2022-08-25 06:21:22 -07:00
David Harris
cb2c0fe027
Minor name cleanups
2022-08-25 04:28:25 -07:00
David Harris
a3828420c0
Replaced dtim with rom-based IROM in IFU. Moved cache control signals out of DTIM and IROM
2022-08-25 04:06:27 -07:00
David Harris
fe3147806d
removed simpleram and modified dtim to use bram1p1rw
2022-08-25 03:39:57 -07:00
Ross Thompson
b650d7e05a
Renamed RAM to UNCORE_RAM.
2022-08-24 18:09:07 -05:00
Ross Thompson
c6927d2ace
Modified the lsu/ifu memory configurations.
2022-08-24 12:35:15 -05:00
Ross Thompson
0c52c7f69c
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-08-23 18:52:15 -05:00
Ross Thompson
ee3d968da0
Found small bug in busfsm which was issuing 1 extra memory read after each cache line fetch. Does not appear to have translated to an extra read out of ahblite.
2022-08-23 18:51:11 -05:00
David Harris
27cca2e3fd
Fixed LSU typos
2022-08-23 10:23:08 -07:00
Ross Thompson
b9fadc11c3
Replaced LSU data replication with 0 extention.
2022-08-23 10:43:47 -05:00
Ross Thompson
cd0da2e3b3
Updated the names of the *WriteDataM inside the LSU to more meaningful names.
...
Moved the FWriteDataMux so that the bus and dtim both get fpu stores.
Modified the PMA to disallow double sized reads when XLEN=32.
2022-08-23 10:34:39 -05:00
David Harris
7c91ed38a3
LSU minor edits
2022-08-23 07:35:47 -07:00
David Harris
a9a5285ba8
Named HTRANS states in busfsm
2022-08-22 13:56:46 -07:00
David Harris
34eece10b8
Finished FPU-LSU interface cleanup
2022-08-22 13:43:04 -07:00
David Harris
bf54c1c868
Simplified FPU-LSU interface to skip IEU
2022-08-22 13:29:20 -07:00
Ross Thompson
21526957cf
Updated fpga test bench.
...
Solved read delay cache bug. Introduced during cache optimizations.
2022-08-21 15:59:54 -05:00
Ross Thompson
96d6218078
Possible reduction of ignorerequest.
2022-08-19 18:07:44 -05:00
Ross Thompson
5301444a61
Changed signal names.
2022-08-17 16:12:04 -05:00
Ross Thompson
970a90dd72
Better name for LSUBusWriteCrit. Changed to SelLSUBusWord.
2022-08-17 16:09:20 -05:00
Ross Thompson
c3bd396bdb
Removed old code from interlockfsm.
2022-08-17 12:52:56 -05:00
Ross Thompson
f7e64fcd69
Fixed fstore2 in cache?
2022-08-01 22:04:44 -05:00
Ross Thompson
b8356c7449
Replaced swbytemask with swbytemaskword (1 liner). Credit to David Harris.
2022-08-01 21:12:25 -05:00
Ross Thompson
171cf7413b
Replaced LOGWPL with LOGBWPL (Bus words per line) and LOGCWPL (cache words per line). Replaced with wordlen/8 bytemask.
2022-08-01 21:08:14 -05:00
Ross Thompson
5d9dab6149
pulled swbbytemask out of subword write.
2022-08-01 20:48:45 -05:00
Ross Thompson
f1bd2524b7
Don't use this commit yet. Untested.
2022-07-24 15:40:52 -05:00
Ross Thompson
334008630f
Overlapped read fetch line end with eviction write line start. I'm a bit concerned this is not well tested.
2022-07-24 01:20:29 -05:00
Ross Thompson
5cd6c8069d
signal name cleanup.
2022-07-22 23:36:27 -05:00
Katherine Parry
452b017f9a
found the bug in the store modification
2022-07-12 22:42:19 +00:00
Katherine Parry
ca4fe08fd9
renamed FLoad2 to FStore2
2022-07-09 00:26:45 +00:00
Katherine Parry
cd53ae67d9
moved fpu ieu write data mux to lsu
2022-07-08 23:56:57 +00:00
David Harris
d73645944f
APB CLINT passing regression
2022-07-05 15:51:35 +00:00
Katherine Parry
6baded9121
added rv32 double precision stores - untested
2022-06-28 21:33:31 +00:00
Katherine Parry
254ebf478e
added fld in rv32 - needs testing
2022-06-20 22:53:13 +00:00
slmnemo
98c07ce2c0
Added more comments
2022-06-13 12:26:08 -07:00
slmnemo
3d715a098c
Added comment about name of LSUBusInit/Lock signal
2022-06-13 10:56:02 -07:00
slmnemo
cadd62e49f
Removed irrelevant comments in ahblite and made it more clear when to use certain transmission signals
2022-06-10 20:43:56 -07:00
slmnemo
beb4317e68
Added comments to signals added so the bus is easier to analyze
2022-06-10 20:30:04 -07:00
slmnemo
b7357efc6b
Fixed failed regression state by only enabling counting when doing cached operations
2022-06-10 20:00:09 -07:00
slmnemo
63ed390c90
Fixed error where CntReset would be high one cycle too long, adding a cycle of delay. Broke wally64priv by failing trap-sret-01.
2022-06-10 19:10:01 -07:00
slmnemo
dc11066ff2
Passed Regression: Seems to work perfectly fine
2022-06-09 18:21:13 -07:00
slmnemo
5a6eae214a
?
2022-06-09 17:50:47 -07:00
slmnemo
3e8d3bae88
Changes made on 9th Jun
2022-06-09 17:33:51 -07:00
slmnemo
0d04751c77
Fixed error when doing uncached accesses where HTRANS was always 2
2022-06-08 18:58:07 -07:00
slmnemo
81d373c7ab
Fixed error related to bus being unable to complete a line write after a memory read followed by an idle and cachewrite request.
2022-06-08 17:34:02 -07:00
slmnemo
315c2f0669
Working version: Fixed error where Word count would always increment even without AHB to bus ACK
2022-06-08 15:29:32 -07:00
slmnemo
054cf5f7b0
Reworked AHB fsm to support one cycle latency read and writes, renamed key signals to better reflect their use, and fixed HTRANS errors
2022-06-08 15:03:15 -07:00
slmnemo
284e0395a0
Merge branch 'main' into cacheburstmode
2022-06-08 02:21:33 +00:00
slmnemo
2d76953d42
Added lock signal to ensure AHB speaks with the right bus
2022-06-08 02:19:21 +00:00
slmnemo
6d36150c3d
Fixed off-by-one error in busdp capture
2022-06-07 19:36:39 +00:00
slmnemo
73e0c1c07f
Reworked bus to handle burst interfacing
2022-06-07 11:22:53 +00:00
David Harris
c7ec9282fe
Provided sfencevmaM to hazard unit and renamed TLBFlush signals to sfencevma going into LSU/IFU. Preparing for SFENCE.VMA to flush the pipeline, but that is not yet working.
2022-06-02 14:18:55 +00:00
slmnemo
446ad498aa
Fixed double assignment on LSUBurstType
2022-06-01 01:04:49 +00:00
slmnemo
bc17f883d4
changed ahb FSM and caught potential bug in ack/wordcountthreshold when on last word
2022-05-26 18:41:27 -07:00
slmnemo
847c7930c4
added LSUBurstDone signal to signal when a burst has finished
2022-05-26 16:29:13 -07:00
slmnemo
80fc716cd7
Added signal to monitor HBURST and comments for each burst in busdp
2022-05-26 13:35:49 -07:00
slmnemo
08430a1e85
added burst size signals to the IFU, EBU, LSU, and busdp
2022-05-25 18:02:50 -07:00
David Harris
5670f77de2
More unused signal cleanup
2022-05-12 15:21:09 +00:00
David Harris
e2e63ca9a8
Clean up unused signals
2022-05-12 14:49:58 +00:00
David Harris
04fd22aeb0
endian swapper
2022-05-08 06:51:50 +00:00
David Harris
4f1b0fdc64
Preliminary support for big endian modes. Regression passes but no big endian tests written yet.
2022-05-08 06:46:35 +00:00
David Harris
22842816a8
LSU name cleanup
2022-04-18 03:18:38 +00:00
David Harris
c07b9d1722
Renamed FinalAMOWriteDataM to AMOWriteDataM
2022-04-18 01:30:03 +00:00
David Harris
d8b4c985cd
Remvoed bytemask anding from FinalWriteDataM in subwordwrite
2022-04-17 22:33:25 +00:00
Ross Thompson
bfc68bef69
Fixed possible bugs in LRSC.
2022-04-16 14:45:31 -05:00
Ross Thompson
396f697d2f
Hacky fix to prevent ITLBMissF and TrapM bug.
2022-04-12 17:56:23 -05:00
Ross Thompson
70e207e010
Found the complex TrapM giving back the wrong instruction bug.
...
As I was reviewing the busfsm I found a typo.
assign UnCachedLSUBusRead = (BusCurrState == STATE_BUS_READY & UnCachedAccess & LSURWM[1] & IgnoreRequest) |
(BusCurrState == STATE_BUS_UNCACHED_READ);
It should be
assign UnCachedLSUBusRead = (BusCurrState == STATE_BUS_READY & UnCachedAccess & LSURWM[1] & ~IgnoreRequest) |
(BusCurrState == STATE_BUS_UNCACHED_READ);
There is a ~ missing before IgnoreRequest. I restarted the FPGA and had it trigger on the specific faulting event. Sure enough the bus makes an IFUBusRead, which UncachedLSUBusRead feeds into. The specific instruction in the fetch stage had an ITLBMiss with a physical address in an unmapped area which is interpreted as an uncached operation. IgnoreRequest is is high if there is a TrapM | ITLBMissF. Without the & ~IgnoreRequest the invalid address translation makes the request.
2022-04-11 13:07:52 -05:00
Ross Thompson
e4f4e1bd43
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-03-30 11:09:44 -05:00
Ross Thompson
839bede656
Converted over to the blockram/sram memories. Now I just need to cleanup. But before the cleanup I wan to make sure the FPGA synthesizes with these changes and actually keeps the preload.
2022-03-30 11:04:15 -05:00
David Harris
c4f2c6b110
fpu compare simplification, minor cleanup
2022-03-29 17:11:28 +00:00
Ross Thompson
fe896bff8e
Found a way to remove a bus input into MMU. PAdr can be made into VAdr by selecting the faulting virtual address when writing the DTLB.
2022-03-24 23:47:28 -05:00
Ross Thompson
71aad2d213
Moved WriteDataM register into LSU.
2022-03-23 14:17:59 -05:00
Ross Thompson
8f74fd2a50
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-03-23 14:10:38 -05:00
Ross Thompson
b2487f4b72
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-03-22 21:28:50 -05:00
Ross Thompson
ca8fb45367
Added comment about needed fix to misaligned fault.
2022-03-22 16:52:07 -05:00
Ross Thompson
ee4b38dce3
dtim writes are supressed on non cacheable operation.
2022-03-12 00:46:11 -06:00
Ross Thompson
86cc758354
cleanup of ram.sv
2022-03-11 18:09:22 -06:00
Ross Thompson
67ff8f27f4
Can now support the following memory and bus configurations.
...
1. dtim/irom only
2. bus only
3. dtim/irom + bus
4. caches + bus
2022-03-11 15:18:56 -06:00
Ross Thompson
9dce2a0679
Towards allowing dtim + bus.
2022-03-11 14:58:21 -06:00
Ross Thompson
b7a680ec2a
Moved subcachelineread inside the cache. There is some ugliness to still resolve.
2022-03-11 12:44:04 -06:00
Ross Thompson
a18f06c20b
Moved subcacheline read inside the cache.
2022-03-11 11:03:36 -06:00
Ross Thompson
52cc852600
removed unused parameter.
2022-03-11 10:43:54 -06:00
Ross Thompson
7f0c5cc847
atomic cleanup.
2022-03-10 18:56:37 -06:00
Ross Thompson
257015a2df
Name changes.
2022-03-10 18:50:03 -06:00
Ross Thompson
6d914def08
Name cleanup.
2022-03-10 18:44:50 -06:00
Ross Thompson
63b1ea88c9
Signal name cleanup.
2022-03-10 18:26:58 -06:00
Ross Thompson
1aa87c9f3a
Moved subwordwrite to lsu directory.
2022-03-10 18:15:25 -06:00
Ross Thompson
396c97fc36
Byte write enables are passing all configs now.
2022-03-10 17:26:32 -06:00
Ross Thompson
d8e71e8e35
Progress on the path to getting all configs working with byte write enables.
2022-03-10 17:02:52 -06:00
Ross Thompson
67ef46ea92
Partially working byte write enables. Works for cache, but not dtim or bus only.
2022-03-10 16:11:39 -06:00
Ross Thompson
7a129c75cd
Added byte write enables to cache SRAMs.
2022-03-10 15:48:31 -06:00
Ross Thompson
95bb4cc8a8
Minor cleanup to interlockfsm.
2022-03-08 23:38:58 -06:00
Ross Thompson
0310fe858f
Comments.
2022-03-08 18:05:25 -06:00
Ross Thompson
75e93baaee
Marked signals for name changes.
2022-03-08 17:41:02 -06:00
Ross Thompson
3ec32d7ce8
Removed unused signal.
2022-03-08 16:58:26 -06:00
Ross Thompson
7b96b3f73c
Moved cacheable signal into cache.
2022-03-08 16:34:02 -06:00
David Harris
2cea3349ad
LSU/Cache code review notes
2022-03-04 00:07:31 +00:00
Ross Thompson
15f6871a8d
Added generates to pcnextf muxes for privileged and caches.
2022-02-22 22:45:00 -06:00
Ross Thompson
59f04f2518
Minor busdp cleanup.
2022-02-22 17:28:26 -06:00
Ross Thompson
971dd494f6
Clarified interlockfsm.
2022-02-22 11:31:28 -06:00
Ross Thompson
1ab2e7590b
Added some clearity to lsuvirtmem.sv.
2022-02-21 17:20:58 -06:00
Ross Thompson
ace743ae91
Changed HPTWRead/HPTWWrite to be HPTWRW to be similar to MemRW.
2022-02-21 16:54:38 -06:00
Ross Thompson
414e73edd9
Cleaned up names in lsuvirtmem.
2022-02-21 16:44:30 -06:00
Ross Thompson
456a54166a
Minor cleanup of lsu.
2022-02-21 12:46:06 -06:00
Ross Thompson
5d9ad011d2
Moved mux into lsuvirtmem.
2022-02-21 09:31:29 -06:00
Ross Thompson
a60332b455
Minor changes to LSU.
2022-02-19 14:38:17 -06:00
Ross Thompson
0bd533473c
New config option to enable hptw writes to PTE in memory to update Access and Dirty bits.
2022-02-17 17:19:41 -06:00
