Ross Thompson f1bd2524b7 Don't use this commit yet. Untested.		2022-07-24 15:40:52 -05:00
..
atomic.sv	Clean up unused signals	2022-05-12 14:49:58 +00:00
bigendianswap.sv	added fld in rv32 - needs testing	2022-06-20 22:53:13 +00:00
busdp.sv	?	2022-06-09 17:50:47 -07:00
busfsm.sv	Overlapped read fetch line end with eviction write line start. I'm a bit concerned this is not well tested.	2022-07-24 01:20:29 -05:00
dtim.sv	Converted over to the blockram/sram memories. Now I just need to cleanup. But before the cleanup I wan to make sure the FPGA synthesizes with these changes and actually keeps the preload.	2022-03-30 11:04:15 -05:00
interlockfsm.sv	atomic cleanup.	2022-03-10 18:56:37 -06:00
lrsc.sv	Clean up unused signals	2022-05-12 14:49:58 +00:00
lsu.sv	signal name cleanup.	2022-07-22 23:36:27 -05:00
lsuvirtmen.sv	Found a way to remove a bus input into MMU. PAdr can be made into VAdr by selecting the faulting virtual address when writing the DTLB.	2022-03-24 23:47:28 -05:00
subwordread.sv	added rv32 double precision stores - untested	2022-06-28 21:33:31 +00:00
subwordwrite.sv	Don't use this commit yet. Untested.	2022-07-24 15:40:52 -05:00
swbytemask.sv	LSU name cleanup	2022-04-18 03:18:38 +00:00