Xavi/cvw
1
0
Fork 0
forked from Github_Repos/cvw
Code Issues Pull Requests Packages Projects Releases Wiki Activity
1,773 Commits 14 Branches 1 Tag 31 MiB
4139f27d10
Commit Graph

391 Commits

Author SHA1 Message Date
Noah Boorstin
1b206d5a3c busybear: make a second .do file with better optimization for command line mode 2021-03-08 19:35:00 +00:00
Noah Boorstin
93c9c57426 busybear: load mem files from verilog instead of .do 2021-03-08 19:26:26 +00:00
Ross Thompson
d5f151eb0f Updated the paths to the branch predictor memory preloads for busy bear. 2021-03-05 15:36:00 -06:00
Ross Thompson
87ed6d510c Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-03-05 15:27:22 -06:00
Ross Thompson
301166d062 Oups. I forgot to update other do files with the commands to preload the branch predictor memories. 2021-03-05 15:23:53 -06:00
Noah Boorstin
3c5be59e9b busybear: add branch preditor loading to do file 
(sorry to add more loading to the do instead of less)
 2021-03-05 21:01:41 +00:00
Noah Boorstin
86142e764a Merge branch 'main' into busybear 2021-03-05 20:27:19 +00:00
Noah Boorstin
889d2c0b85 fix wally-pipelined-batch.do to match wally-pipelined.do 2021-03-05 20:27:01 +00:00
bbracker
19fc7d2381 refactored sim file 2021-03-05 14:25:16 -05:00
bbracker
0f4a231543 first merge of ahb fix 2021-03-05 14:24:22 -05:00
Noah Boorstin
5a3ba1174e busybear: better implenetation of sim-busybear-batch 2021-03-05 00:39:03 +00:00
Noah Boorstin
dfae278ffb busybear: make imperas tests work again 2021-03-04 22:44:49 +00:00
Jarred Allen
106718b196 Remove rd2, working for non-compressed 2021-03-04 16:46:43 -05:00
Noah Boorstin
827dfd774b Merge branch 'main' into busybear 
Conflicts:
	wally-pipelined/src/uncore/imem.sv
 2021-03-04 20:16:03 +00:00
Ross Thompson
66e84f3a2c Merge branch 'bp' into main 
Concerns:
1. I don't think the correct data buses are going to the multiplier.
2. I'm not sure the FlushF signal is correct.
 2021-03-04 13:35:46 -06:00
Teo Ene
8f1584ca04 Edited assemby of bare-metal coremark to make it run 2021-03-04 07:45:40 -06:00
Teo Ene
396dc61564 Linux CoreMark and baremetal CoreMark split into two separate tests/configs 2021-03-04 07:44:33 -06:00
Teo Ene
6ebb79abe0 Linux CoreMark is operational 2021-03-04 05:58:18 -06:00
Teo Ene
08a7f6ec25 In the process of updating coremark.RV64I program to work with Dr. Harris's perl script. Commiting to make it easier to switch branches 2021-03-04 01:27:05 -06:00
Teo Ene
6031269de8 Implemented fix disucssed with Elizabeth 2021-03-03 18:17:53 -06:00
Teo Ene
37bf3d836f Updated coremark .do file for easier debugging 2021-03-03 15:10:39 -06:00
Teo Ene
e7f7f980b3 Updated coremark .do file for easier debugging 2021-03-02 17:23:39 -06:00
Noah Boorstin
21b1c4163c busybear: add sim-busybear and sim-busybear-batch based on sim-wally 2021-03-01 21:01:15 +00:00
Noah Boorstin
62b441f3f5 busybear: probably discovered bug in ahb code 2021-03-01 20:56:04 +00:00
Noah Boorstin
4833b36535 busybear: more adapting to new memory system 2021-03-01 18:50:42 +00:00
Noah Boorstin
26d4024b33 busybear: fix bootram range 2021-03-01 17:45:21 +00:00
Noah Boorstin
bcc0010498 Merge branch 'main' into busybear 2021-02-28 20:45:08 +00:00
Noah Boorstin
f306d2d2e1 busybear: start preloading bootmem 2021-02-28 20:43:57 +00:00
Noah Boorstin
db86d20d11 busybear: check instead of providing InstrF 2021-02-28 16:46:53 +00:00
Ross Thompson
7592a0dacb Shreya and I found a bug with the exeuction of JAL and JALR instructions. The link was only set in the writeback stage. Once the branch predictor started correctly predicting JAL(R)s the ALU and forwarding logic need to have the PCLinkE at the execution stage in case an instruction in the next two clocks need the data. 2021-02-26 20:12:27 -06:00
Ross Thompson
37e6a45d76 Updating the test bench to include a function radix. Not done. 2021-02-26 19:43:40 -06:00
David Harris
cf03afa880 Eliminated flushing pipeline on CSR reads 2021-02-26 17:00:07 -05:00
kaveh pezeshki
c7863d58cd merged with main to integrate with AHB 2021-02-26 05:37:10 -08:00
Noah Boorstin
ab9247d625 busybear: add main ram loading, better instr checking also 2021-02-26 20:26:54 +00:00
Teo Ene
c47872c2af Changed .do file back to run all 2021-02-25 09:58:54 -06:00
David Harris
d00d42cf9a Merged bus into main 2021-02-25 00:28:41 -05:00
Teo Ene
3e5de35fc4 Added provisional coremark files from work with Elizabeth 2021-02-24 20:07:07 -06:00
Noah Boorstin
3d82ceffb7 busybear: preload bootram 
thanks to Prof Stine for the .do file commands

@kaveh can you check line 201? it does nothing, but things break when
I remove that line
 2021-02-24 18:46:09 +00:00
Noah Boorstin
00605864fc busybear: start adding ram 2021-02-23 22:01:23 +00:00
Noah Boorstin
ceb7df3561 busybear: instantiate soc instead of hart 2021-02-23 18:59:06 +00:00
kaveh pezeshki
62d9185212 Merge remote-tracking branch 'origin/tlb_toy' into busybear 2021-02-22 02:23:01 -08:00
Ross Thompson
9b3637bd87 RAS needs to be reset or preloaded. For now I just reset it. 
Fixed bug with the instruction class.
Most tests now pass.  Only Wally-JAL and the compressed instruction tests fail.  Currently the bpred does not support compressed.  This will be in the next version.
 2021-02-19 20:09:07 -06:00
Ross Thompson
00de91cc87 Added FlushF to hazard unit. 
Fixed some typos with the names of signals in the branch predictor.  They were causing signals to be not set.  Note there is a modelsim flag which prevents it from compiling if a logic is undefined.
I will look this up and add it to the compiler.
 2021-02-19 16:36:51 -06:00
Ross Thompson
f25de68b7d minor change to wave file. 2021-02-19 09:08:13 -06:00
Ross Thompson
c6ebe7733b Hacked the sram memory models to reset their internal registers. This allows the simulation to run but is only temporary. 
About 149307ns of simulation run.
 2021-02-18 21:32:15 -06:00
Ross Thompson
de9e383bc6 Wrote a bash script to generate custom modelsim radix which maps instruction addresses into human readable lables. 
Once combined with some simulation verilog this will display the current function in modelsim.
 2021-02-17 22:20:28 -06:00
Ross Thompson
5df7e959f3 Integrated the branch predictor into the hardward. Not yet working. 2021-02-17 22:19:17 -06:00
Noah Boorstin
7312da1a99 busybear: allow testbench to ignore lack of MMU for now 
I'd really like to go over this with someone else, not sure if this is
a good thing to be doing

If it is, we're at 1M instructions!
 2021-02-12 20:08:56 +00:00
bbracker
9231646fb3 bus rw bugfix and peripherals testing 2021-02-12 00:02:45 -05:00
Teo Ene
8a6de4fb86 Adding coremark testbench and do files that Elizabeth has written thus far, on this account, in order to avoid merge conflicts 2021-02-10 20:48:39 -06:00
David Harris
2357f5513b Debugging instruction fetch 2021-02-09 11:02:17 -05:00
David Harris
3551cc859b Data memory bus integration 2021-02-07 23:21:55 -05:00
Noah Boorstin
01c0f9db63 Busybear: next week of updates 
- move parsed instructions out of git, to /courses/e190ax/busybear_boot
 - parsed first 1M instructions, and now parse from split GDB runs
 - now at about 230k instructions, can't progress further for now since atomic instructions
   aren't implemented yet
 2021-02-07 03:14:48 +00:00
Noah Boorstin
14cde0d59c Change CSR reset and available bits to conform to OVPsim 
Now actually keeping perfectly in line with OVP for the first 100k instrs. Yay.
 2021-02-04 22:03:45 +00:00
Jarred Allen
ea791cb057 Change busybear test to use work-busybear library 2021-02-03 11:12:47 -05:00
Jarred Allen
10f023b44d Refactor regression test 2021-02-02 17:22:29 -05:00
Noah Boorstin
b370be4a8a Add busybear testbench to nightly regression checking 
If you don't like how I did this please feel free to undo it
 2021-02-02 22:05:35 +00:00
Jarred Allen
5090537f3c Fix intermittent errors caused by weird library stuff 2021-02-02 11:20:09 -05:00
Jarred Allen
2b75e38239 Fix issues in parallel regression testing 2021-02-01 23:29:03 -05:00
Noah Boorstin
ff88214730 busybear: change register file checking to only store register changed 
this should make parsedRegs.txt much smaller
 2021-02-02 01:27:43 +00:00
Jarred Allen
84801213d6 Parallelize regression-wally.p 2021-02-01 15:40:27 -05:00
Noah Boorstin
b7f63c1dc7 busybear: NOP out floating point instructions for now 
Why does linux even try to do float stuff doing booting??
also, now runs the first 100k instructions!
 2021-01-30 19:52:47 +00:00
Noah Boorstin
4358f086be update busybear testbench to conform to new structure 
aaaaaaaaaaaaaaaaaahhhh so many changes

also the testbench now uses another internal signal,
which I don't like, but I can't think of a better option rn
 2021-01-30 19:19:00 +00:00
David Harris
396cea1ea7 Reorganized src hierarchically 2021-01-30 11:50:37 -05:00
David Harris
a357f2a0e7 Connected AHB bus to Uncore 2021-01-29 23:43:48 -05:00
David Harris
8d4f5277d2 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-01-29 15:38:01 -05:00
David Harris
dc2443c55b Moving data memory to uncore 2021-01-29 15:37:51 -05:00
Noah Boorstin
194d5b55ab update busybear testbench to conform to new structure 2021-01-29 17:46:50 +00:00
Noah Boorstin
8ab5879af5 busybear testbench: test on first 100k instrs 
currently gets about 47k instrs correctly
also fix gdb parsing to avoid accidently matching on function names
 2021-01-29 00:14:23 -05:00
Noah Boorstin
619dec1490 busybear: simulate first 10k instructions 
I know we need to add CSR checking sometime soon
Also I'm a bit sketpical this is all working properly, and that no new bugs
were uncovered from 1k instrs to 10k instrs
 2021-01-28 19:44:58 -05:00
Noah Boorstin
4f84bd3c8f busybear: fix misaligned writing checking 2021-01-28 19:35:09 -05:00
Noah Boorstin
beb93e2508 busybear: add more test instructions 
currently testing first 1k instrs
 2021-01-28 16:41:37 -05:00
Noah Boorstin
91e9defd0a more of the same fixes 2021-01-28 16:26:15 -05:00
Noah Boorstin
623d9feeab more misaligned read fixing 
I'm getting fairly concerned about this, I feel like
this should only work if the memory ignores the lower 3 or 4 bits of the adr
 2021-01-28 16:14:35 -05:00
Noah Boorstin
405c9d90b5 busybear testbench: understand bytemask for writes 2021-01-28 15:42:47 -05:00
Noah Boorstin
a4bac85ece busybear: ret is only 1 word 2021-01-28 14:47:40 -05:00
Noah Boorstin
0befdfacec add speculative exception for compressed instructions 2021-01-28 14:40:35 -05:00
Noah Boorstin
27142f0fef testbench now understands lw not aligned to 8 bytes 
also busybear now has first 500 instead of 100 instrs
and prints current instrs less
 2021-01-28 13:33:22 -05:00
Noah Boorstin
206747b8b2 Busybear test now processes first 100 instrs correctly! 
- changed test parser to recognize lw in addition to lw

also, added temporary questa files (wlft*) to .gitignore
 2021-01-28 01:19:27 -05:00
Noah Boorstin
8f6994196a fix memory write address decoding for busybear tests 2021-01-28 01:19:26 -05:00
Noah Boorstin
28fabb94ee update busybear testbench to conform to new structure 2021-01-27 23:42:19 -05:00
David Harris
4df461ad77 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-01-27 22:49:55 -05:00
David Harris
824014c5c0 Repartitioned with Instruction Fetch Unit, Integer Execution Unit 2021-01-27 22:49:47 -05:00
Noah Boorstin
c9baa70e26 update busybear testbench to conform to new structure 2021-01-27 12:54:09 -05:00
David Harris
e84fbd0a73 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-01-27 06:40:39 -05:00
David Harris
b88508ca11 Repartitioned datapath and controller into ieu 2021-01-27 06:40:26 -05:00
Noah Boorstin
1195ebb468 show instruction assembly in waveform 2021-01-26 12:34:12 -05:00
Noah Boorstin
6c567aab9a Update busybear tests to conform to new directory structure 2021-01-25 20:37:18 -05:00
Noah Boorstin
e92db93939 Fixed mem write checking 
now passes around 50 instructions!
 2021-01-25 20:07:08 -05:00
Noah Boorstin
358393a1da fix speculation ignoring for PC fetching 2021-01-25 20:07:06 -05:00
David Harris
fa18052348 Added test configurations 2021-01-25 11:28:43 -05:00