Ross Thompson
31d5eabd77
Renamed Word to Beat for ahbcacheinterface.
2022-11-09 17:52:50 -06:00
Ross Thompson
3653d6b3ed
Renamed CACHE_EVICT to CACHE_WRITEBACK.
2022-11-09 17:43:06 -06:00
Ross Thompson
42c0a10d07
Removed TrapM from the LSU and IFU. TrapM is replaced with FlushW for both. (Don't like this for the IFU).
...
FlushW prevents writting the cache, dtim, and bus state. FlushW still gates HTRANS.
FlushW does not impact the mealy outputs of the cache and bus FSMs and hazard is updated to
not stall W if we get a trap.
2022-11-07 15:50:55 -06:00
Ross Thompson
922513c22f
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-11-07 09:10:51 -06:00
cturek
b137a95a35
propagated otfc swap to Rad2 and 4 qslc
2022-11-06 23:32:38 +00:00
Ross Thompson
8d57e488c8
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-11-06 17:22:25 -06:00
cturek
1e927df1a0
Added conditional OTFC swap for simplified int postprocessing
2022-11-06 23:09:09 +00:00
cturek
56b7bb3590
Finished Int Preprocessinggit add ../src/fpu/fdivsqrt/fdivsqrtpreproc.sv
2022-11-06 22:40:21 +00:00
cturek
ee048325cb
Added n and rightshiftx
2022-11-06 22:31:48 +00:00
cturek
67f2cb0595
p calculation
2022-11-06 22:24:21 +00:00
cturek
7567f388c2
Changed lzc names, started int/fp size merge in preproc
2022-11-06 22:21:35 +00:00
cturek
333da5c945
Added n, p, and m signals between fdivsqrt submodules. Added w64 and mdue to divsqrt testbench.
2022-11-06 22:08:18 +00:00
cturek
b893d9249d
Added new macros for int div preprocessing, added p, n, and rightshiftx logic
2022-11-06 21:53:48 +00:00
David Harris
c78643f4e4
Reorder embench tests to prevent crash
2022-11-04 15:21:51 -07:00
David Harris
e57083a0ef
HPTW cleanup
2022-11-04 15:21:09 -07:00
Ross Thompson
977ad1c33c
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-11-04 13:30:08 -05:00
cturek
39bf6a456e
renamed remOp to RemOp
2022-11-03 22:37:25 +00:00
cturek
890b26466f
Added rem/div operation to postprocessor
2022-11-02 17:49:40 +00:00
Ross Thompson
98d4929c57
Reduced complexity of logic supressing cache operations.
2022-11-01 15:23:24 -05:00
cturek
2a45787b37
Added buffered signals for int/fp
2022-10-28 21:47:24 +00:00
cturek
2ae0a9bb5d
Config Cleanup
2022-10-27 22:38:56 +00:00
Ross Thompson
03f68a4cf5
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-10-26 14:48:50 -05:00
Ross Thompson
36d9a00471
Fixed the uart transmit fifo overrun bug.
2022-10-26 14:48:09 -05:00
cturek
51fc4de0e1
small signal cleanup
2022-10-26 18:42:49 +00:00
cturek
544c142c4f
abs for int inputs
2022-10-26 16:18:05 +00:00
cturek
e401d12889
Added signed division to fdivsqrt
2022-10-26 16:13:41 +00:00
cturek
a8a89f8dfc
unbroke DIVb
2022-10-26 16:11:51 +00:00
cturek
8475de128b
Config cleanup
2022-10-25 21:04:09 +00:00
Jacob Pease
ec0cede2f2
Added PLIC signals for debugging on FPGA.
2022-10-25 13:57:09 -05:00
cturek
94daa961b3
Started Integer Preprocessing
2022-10-25 17:48:43 +00:00
Ross Thompson
1510c2d92f
Setup to run with both the vcu108 and vcu118 boards. Set the parameters in the Makefile.
2022-10-24 15:38:39 -05:00
Ross Thompson
cc605a1966
Bit width error.
2022-10-24 13:48:47 -05:00
Ross Thompson
270a83352f
Found a way to remove the interlock fsm. Dramatically reducing the complexity of virtual memory and page table walks.
2022-10-23 13:46:50 -05:00
Ross Thompson
54bd1fb806
Small cleanup of interlockfsm.
2022-10-22 16:29:51 -05:00
Ross Thompson
ae7a71c0f4
Created one off test to replicate the floating point forwarding hazard bug.
2022-10-22 16:29:12 -05:00
Ross Thompson
f9a04c13df
comment updates.
2022-10-22 16:28:44 -05:00
Ross Thompson
78586c5a7a
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-10-22 16:27:30 -05:00
Ross Thompson
611ea6882d
Changed FDivBusyE to stall the whole pipeline. Any instruction in the Executation which depended on the output of an instruction in the writeback stage would be lost if the back end of the pipelined advanced. The solution is to stall the whole pipeline.
2022-10-22 16:27:20 -05:00
Jacob Pease
1f207bcafb
Extended rxfifotimeout count to actually be 4 characters long.
2022-10-20 17:35:49 -05:00
Ross Thompson
e5cae3bfa0
Moving interlockfsm changes to a temporary branch.
...
reduced complexity of cache mux controls.
2022-10-19 15:08:23 -05:00
Ross Thompson
5ad3ee6b54
Broken don't use this state.
2022-10-19 14:31:22 -05:00
Ross Thompson
de1e569ee9
Noted possible bug with endianness during hptw.
...
Minor complexity reduction in interlockfsm. I think there is a lot of room to simplify.
2022-10-19 12:20:19 -05:00
Ross Thompson
a58179b1d6
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-10-19 10:42:31 -05:00
Ross Thompson
49a85c7f50
Sort of solved the bit width warning for dtim, irom ranges.
2022-10-19 10:42:19 -05:00
Ross Thompson
61f7bad739
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-10-18 15:06:09 -05:00
Ross Thompson
962ba5e4b8
Updated uart settings and fpga wave config.
2022-10-18 15:05:33 -05:00
Ross Thompson
a7ae593a68
Possible fix for interrupt during a floating point divide.
2022-10-18 15:04:21 -05:00
Ross Thompson
2c80c2b35f
Merged cacheable with seluncachedadr.
2022-10-17 13:29:21 -05:00
David Harris
6ab6467777
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-10-14 17:33:36 -07:00
David Harris
1428081742
Removed unused FPU waves
2022-10-14 17:33:32 -07:00
