Ross Thompson 611ea6882d Changed FDivBusyE to stall the whole pipeline. Any instruction in the Executation which depended on the output of an instruction in the writeback stage would be lost if the back end of the pipelined advanced. The solution is to stall the whole pipeline.		2022-10-22 16:27:20 -05:00
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config	Modified the do scripts to change the DTIM_RANGE and IROM_RANGE to large values from the defaults.	2022-10-11 10:47:13 -05:00
misc	Renamed wally-pipelined to pipelined	2022-01-04 19:47:41 +00:00
regression	Sort of solved the bit width warning for dtim, irom ranges.	2022-10-19 10:42:19 -05:00
src	Changed FDivBusyE to stall the whole pipeline. Any instruction in the Executation which depended on the output of an instruction in the writeback stage would be lost if the back end of the pipelined advanced. The solution is to stall the whole pipeline.	2022-10-22 16:27:20 -05:00
testbench	fixed endianness mstatush problem, passes make, not regression	2022-10-04 17:37:39 +00:00