Ross Thompson
61f7bad739
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-10-18 15:06:09 -05:00
Ross Thompson
962ba5e4b8
Updated uart settings and fpga wave config.
2022-10-18 15:05:33 -05:00
Ross Thompson
a7ae593a68
Possible fix for interrupt during a floating point divide.
2022-10-18 15:04:21 -05:00
Ross Thompson
2c80c2b35f
Merged cacheable with seluncachedadr.
2022-10-17 13:29:21 -05:00
David Harris
6ab6467777
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-10-14 17:33:36 -07:00
David Harris
1428081742
Removed unused FPU waves
2022-10-14 17:33:32 -07:00
amaiuolo
a0712d1456
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally
2022-10-13 22:36:57 +00:00
amaiuolo
000117fcd4
added amaiuolo@hmc.edu
2022-10-13 22:36:52 +00:00
Ross Thompson
47915421c2
Fixed uncached read bug introduced by yesterday's changes.
2022-10-13 11:11:36 -05:00
Ross Thompson
fccaad7f3f
Fixed LSU to correctly handle the difference between LLEN and AHBW.
2022-10-12 12:06:15 -05:00
Ross Thompson
12a6a9f83b
Actually fixed the bus width issue coming out of the cache.
...
The root cause is the ahb bus width can be different from LLEN.
If we switch the d-cache to outputing LLEN and on LLEN intervals, subword read needs to operate on LLEN as well.
Then the cache always outputs LLEN data which may need to be muxed down into 2 or more subwords if ABHW is smaller than LLEN.
2022-10-12 11:33:10 -05:00
Kip Macsai-Goren
f711eb0bcf
quick fix to endianness wapping 64 bit reads in 32 bit confgs
2022-10-11 23:08:02 +00:00
Ross Thompson
b2f71b8255
Modified LSU to support DTIM without CSRs.
2022-10-11 14:05:20 -05:00
Ross Thompson
a5c15fd801
Fixed first problem with the rv64i IROM.
2022-10-11 11:35:40 -05:00
Ross Thompson
403daecc8e
Modified the do scripts to change the DTIM_RANGE and IROM_RANGE to large values from the defaults.
...
The defaults are used for synthesis.
rv64i and rv32i: DTIM 2KiB, IROM 2KiB
rv32ic: DTIM 4KiB, IROM 16KiB
Regression tests require 8MiB or larger so modelsim overrides.
2022-10-11 10:47:13 -05:00
David Harris
36c0e1d4e9
Removed imperas tests from rv32i/rv64i because the configs lack privileged support expected in the tests. Also cleaned up comment in LSU
2022-10-10 10:22:12 -07:00
David Harris
e4c5754b3a
Made simple RV64 configuration be RV64i. Eliminated rv64ic and rv64fp. Fixed some bugs related to new width
2022-10-10 09:10:55 -07:00
David Harris
a5a922d048
Removed unnecessary configuration conditions from subwordread sign extension/NaN boxing
2022-10-10 07:12:37 -07:00
David Harris
849d6d4297
Changed SNPS license server
2022-10-10 06:59:11 -07:00
Ross Thompson
1bc5f88e4a
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-10-09 16:46:51 -05:00
Ross Thompson
b52f593ecb
Reorganized the configs.
2022-10-09 16:46:48 -05:00
David Harris
6092ca757a
New fdivsqrtqsel4cmp module based on comparators rather than table lookup
2022-10-09 04:47:44 -07:00
David Harris
dceb6f9034
Moved shift into divsqrt stage and cleaned up comments
2022-10-09 04:45:45 -07:00
David Harris
55e4911cf0
fdivsqrt code cleanup
2022-10-09 03:37:27 -07:00
Ross Thompson
382ccf74a5
Cleaned up the new muxes to select between IROM/ICACHE/BUS and DTIM/DCACHE/BUS.
2022-10-05 15:46:53 -05:00
Ross Thompson
62951ec653
Fixed wally32e.
2022-10-05 15:37:01 -05:00
Ross Thompson
2144343c4a
Name clarifications.
2022-10-05 15:36:56 -05:00
Ross Thompson
2e578eb8d8
Fixed bug with combined dtim+bus.
2022-10-05 15:16:01 -05:00
Ross Thompson
b52ab91028
Possibly have working dtim + bus config.
2022-10-05 15:08:20 -05:00
Ross Thompson
8d01cf32fc
Updated wavefile.
2022-10-05 14:55:40 -05:00
Ross Thompson
a0c5833d6d
Fixed bug in EBU.
2022-10-05 14:51:12 -05:00
Ross Thompson
68aa1434b4
Modified the LSU and IFU to allow concurrent DTIM/DCACHE+BUS and IROM/ICACHE+BUS.
...
Don't use this commit as the rv32i tests are not passing.
2022-10-05 14:51:02 -05:00
Ross Thompson
20546857e6
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-10-05 14:03:44 -05:00
David Harris
f318daa605
Changed RV32i config to use DTIM and bus. Don't use this commit - it will break rv32i tests.
2022-10-05 11:46:52 -07:00
Ross Thompson
e6b36d0c02
Optimized the ebu's beat counting.
2022-10-05 10:58:23 -05:00
Ross Thompson
9e2cfadd7d
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-10-04 17:39:26 -05:00
Ross Thompson
c21c71d53d
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-10-04 17:39:14 -05:00
Ross Thompson
3f59ea6b6d
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-10-04 17:38:49 -05:00
Ross Thompson
92d7be645b
Reordered the eviction and fetch in cache so it follows a more logical order.
2022-10-04 17:36:07 -05:00
Ross Thompson
8f18bb9243
Updated constraints file to work with alternate uart.
2022-10-04 17:35:44 -05:00
Ross Thompson
52e8e0f5ef
Modified cache lru to not have the delayed write.
2022-10-04 15:14:58 -05:00
Kip Macsai-Goren
d5cd67cf09
fixed endianness mstatush problem, passes make, not regression
2022-10-04 17:37:39 +00:00
Kip Macsai-Goren
2bbcec680f
addded renamed file
2022-10-04 17:37:05 +00:00
Kip Macsai-Goren
c4441eb0fa
Merge branch 'main' of github.com:davidharrishmc/riscv-wally
2022-10-04 17:33:54 +00:00
Kip Macsai-Goren
175e824a61
Renamed endianswap to match module name
2022-10-04 17:33:49 +00:00
Ross Thompson
56cc04316c
Fixed a very subtle bug in the trap handler. It was possible to select the wrong cause if an interrupt was pending, but it was supressed by Committed and another exception triggered.
2022-10-02 16:21:21 -05:00
Ross Thompson
02ed8fc301
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-10-01 15:01:22 -05:00
Ross Thompson
bc94f4aef1
Disable IFU bus access on TrapM.
2022-10-01 14:54:16 -05:00
Ross Thompson
e6db1c5cf8
Added logic to not implement the save/restore muxes for LSU in the EBU's controller input stage.
2022-09-29 18:37:34 -05:00
David Harris
fc4146f409
Adding start signals for integer divider to fdivsqrt
2022-09-29 16:30:25 -07:00
