Rose Thompson
fc62f80407
Closer to fully working hardware tracer.
2024-06-04 11:31:05 -05:00
Rose Thompson
80f98b3223
now have a working ethernet daemon to collect frames and partially decode into RVVI.
2024-06-04 10:20:51 -05:00
Rose Thompson
dc904cdbbb
The ethernet frame is mostly formatted correctly. Just need to reverse the byte order in the Ethernet length/type field.
2024-06-03 18:10:25 -05:00
Rose Thompson
a830bd57f0
Have to reverse the byte order for ethernet frame length.
2024-05-31 17:46:43 -05:00
Rose Thompson
e05ebc30b8
Almost worked out the bugs in packetizer.
2024-05-31 16:48:41 -05:00
Rose Thompson
0dccc6051d
draft of receiving code to unpack the ethernet frames into rvvi.
2024-05-31 13:55:25 -05:00
Rose Thompson
1df3e5239a
This is great. The FPGA is able to send ethernet frames consisting of the RVVI data to the host computer.
...
wireshark is able to capture the frames and they match the expected data!
2024-05-30 17:57:28 -05:00
Rose Thompson
ca90c6ba48
Added the ethernet files. These are part of another repo.
...
We should remove before mainlining this.
2024-05-30 16:33:49 -05:00
Rose Thompson
9703055758
The FPGA is synthesizing with the rvvi and ethernet hardware.
2024-05-30 15:37:17 -05:00
Rose Thompson
dc09e1c0c5
Modified names so they don't conflict with FPGA's axi signals.
2024-05-24 16:38:47 -05:00
Rose Thompson
73261e7f89
More cleanup. Close to the simpliest it can be.
2024-05-24 16:34:33 -05:00
Rose Thompson
bd2ec879d2
Removed unused axi signals from packetizer.
2024-05-24 16:31:27 -05:00
Rose Thompson
263be86119
Packetizer cleanup.
2024-05-24 16:27:09 -05:00
Rose Thompson
1f7d732dca
Moved the rvvisynth code to testbench since I only want this for simulation and fpga.
2024-05-24 16:10:58 -05:00
Rose Thompson
d341974c5b
Have rvvi to ethernet working.
...
Now it is time to move the hardware to the FPGA.
Ideally I don't want Wally to actually have any of this code since it's entirely
debug code so it will move to the fpga/src directory.
Then we'll need to add additional logic to the mmcm to generate the correct clocks.
Finally we'll update the I/O to add ethernet.
2024-05-24 15:52:13 -05:00
Rose Thompson
bf9f45d319
We have a simulation of the ethernet transmission working.
...
This commit does not include the source files for the ethernet as it does not belong to cvw.
I'll want to fork that repo and make it a submodule as I need to change the source a bit.
2024-05-24 11:25:42 -05:00
Rose Thompson
e5b8fd35b0
Successfully added RVVIStall for back pressure to slow down the pipeline if the ethernet or host computer running imperasDV can't keep up.
2024-05-22 09:56:12 -05:00
Rose Thompson
b116c0c902
Lots of progress on the rvvisynth to ethernet packetizer.
...
Almost producing axi4 commands.
2024-05-21 18:23:42 -05:00
Rose Thompson
d1141237ee
Removed prefix from rvvi hierarchy so it works without testbench.
2024-05-21 16:20:53 -05:00
Rose Thompson
8fd278b322
Fixed some references to rvvi.
2024-05-21 16:15:05 -05:00
Rose Thompson
ea5d780adf
Closer to synthesized rvvi
2024-05-21 12:42:43 -05:00
Rose Thompson
b127c19242
Merge branch 'main' into rvvi
2024-05-20 16:31:06 -05:00
Jordan Carlin
1d8ffee20c
Certain Zcb instructions are dependent on other extensions, not the entire extension
2024-05-15 19:16:43 -07:00
Jordan Carlin
3df5a5abdd
Remove additional bitwise operator
2024-05-15 09:29:54 -07:00
Rose Thompson
e295454948
Merge pull request #798 from jordancarlin/newConfig
...
Update config to derive MISA from macros and update MISA bits based on the spec
2024-05-15 10:28:44 -05:00
Jordan Carlin
291d1e62d5
M implies Zmmul
2024-05-14 19:38:34 -07:00
Jordan Carlin
4a72922087
update config to derive MISA from macros
...
- Remove C_SUPPORTED and update decompress unit based on Zc* extensions
- Derive A_SUPPORTED from A subextensions
- Derive B_SUPPORTED from B subextensions
- Derive C_SUPPORTED from C subextensions
2024-05-14 06:49:18 -07:00
David Harris
175c18da01
Parameterized FMA. However, some offsets are not parameterized. See PR #793 for list of changes
2024-05-13 15:16:00 -07:00
David Harris
2dfada0687
Started parameterizing FMA
2024-05-13 14:01:36 -07:00
David Harris
c2b9e326ca
Fround cleanup
2024-05-13 13:27:29 -07:00
David Harris
e87a269f59
Fix fcvt.lu.s bug and lint issue in packoutput
2024-05-12 11:31:27 -07:00
David Harris
380d88fc68
Merged config-shared after fma fix
2024-05-12 11:10:55 -07:00
David Harris
009d251433
Fixed cvtint bug by adding 2 bits to convert width; initial implementation of fround passes basic regression but fails some nightly regression cases
2024-05-11 22:32:51 -07:00
Katherine Parry
807ef44772
fixed fma testfloat issue #578
2024-05-10 18:12:11 -07:00
Rose Thompson
b027fa44ef
Merge branch 'main' of https://github.com/openhwgroup/cvw
2024-05-10 08:53:00 -05:00
Rose Thompson
10b08f8039
Updated brach predictor names to more logical names and match textbook.
2024-05-10 08:51:12 -05:00
David Harris
77137f0f60
ZAAMO and ZALRSC implemented but not tested
2024-05-07 16:45:49 -07:00
David Harris
fcd75fd6b6
Fixed shiftcorrection typo causing failure on testfloat fcvt tests
2024-05-07 14:27:44 -07:00
David Harris
bdc2ad494f
Shared AND gate in ALU for extract / and paths
2024-05-03 09:07:33 -07:00
David Harris
4d5ac3b869
Turned off BMUSubArith for bext/bexti
2024-05-03 08:59:40 -07:00
David Harris
4639e92fda
Turned off BMUSubArith for bext/bexti
2024-05-03 08:56:14 -07:00
David Harris
c0afb44ed4
Tied dangling signals to 0 for some configs to make VCS lint happy
2024-04-28 22:50:36 -07:00
David Harris
7695ad4755
More fround stub code to keep VCS happy
2024-04-28 22:21:51 -07:00
David Harris
06e34b7be4
Fixed byte enables for synthesis
2024-04-27 06:25:24 -07:00
David Harris
1274ec55af
Resolved merge conflict
2024-04-26 16:15:23 -07:00
David Harris
4faf44c4c6
Named zknde block in bitmanipalu
2024-04-25 17:24:00 -07:00
Rose Thompson
6c0b860742
Fixed the cache miss counter.
2024-04-24 16:14:51 -05:00
David Harris
235a3dcfca
ROM preload compatible with Verilator lint, sim, and Design Compiler
2024-04-24 08:44:37 -07:00
David Harris
32b6e6a8ab
fround progress
2024-04-24 04:42:47 -07:00
David Harris
6415bfc3c2
Code and testbench cleanup
2024-04-23 10:17:44 -07:00
