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175 Commits

Author SHA1 Message Date
Rose Thompson
ab750e150f Fixed lint errors for alignment. 2024-02-23 14:00:19 -06:00
Rose Thompson
e84b7cc147 Cleanup. 2024-02-23 13:00:21 -06:00
Rose Thompson
caac48b7f2 Removed duplicate endianswap. 2024-02-23 09:42:39 -06:00
Rose Thompson
a402883115 Simplifications of subword code. 2024-02-23 09:41:59 -06:00
Rose Thompson
fbc18abaa0 Siginficant cleanup of subwordwritemisaligned. 2024-02-22 14:17:15 -06:00
Rose Thompson
45c30267a5 Cleanup. 2024-02-22 14:08:04 -06:00
Rose Thompson
69d31d50e2 Updated subword misaligned. 2024-02-22 13:29:39 -06:00
Rose Thompson
7e1ea1e6d9 Beginning subword cleanup. 2024-02-22 09:37:16 -06:00
Rose Thompson
1ece6f8eae Swapped to the more compact subwordreadmisaligned.sv. 2024-02-22 09:34:16 -06:00
Rose Thompson
3714b2bf4a Non-ideal fix. Added new output from pma which indicates if the write shift should occur. 
The more ideal solution would be to have the pma indicate if the shift should occur and the maximum amount..
 2024-02-22 09:14:43 -06:00
Rose Thompson
6a9c2d8dc4 Closer to getting subword write misaligned working. 2024-02-20 20:23:42 -06:00
Rose Thompson
dac8fc16af Partially working optimized subwordwrite for misaligned. 2024-02-19 12:26:29 -06:00
Rose Thompson
1fd678b433 Optimized the align logic for loads. 2024-02-14 12:14:19 -06:00
Rose Thompson
e900bb09db Merge branch 'main' of https://github.com/openhwgroup/cvw 2024-02-01 12:12:05 -06:00
David Harris
1c62c5e433 Fixed logic to work with FLEN < XLEN 2024-01-31 20:24:16 -08:00
Rose Thompson
aa15a63d9c Merge branch 'main' of https://github.com/openhwgroup/cvw 2024-01-31 13:12:32 -06:00
David Harris
f37c7bb1f6 Incorporated RAM_LATENCY and BURST_EN as parameters rather than define in code. Still need to update testbench to use this 2024-01-30 06:27:18 -08:00
David Harris
45e2317636 Added Wally github address to header comments 2024-01-29 05:38:11 -08:00
Rose Thompson
81d006536a Lint passes with 32-bit no D$, but many regressions fail. 2024-01-18 09:48:44 -06:00
Rose Thompson
ff6bb3be0c Fixed another bug with virtual memory and no caches. 2024-01-18 09:29:52 -06:00
Rose Thompson
e8474373e4 Fixed it so Virtual Memory work without a D$. 2024-01-18 09:18:17 -06:00
Rose Thompson
dfe5ef4427 Added logic for the non-cache atomics. 2024-01-15 17:47:17 -06:00
Rose Thompson
82a786f185 Hmm. Verilator is complaining about the parameter width. I'm not sure why so I changed to 1 bit. 2024-01-15 17:36:01 -06:00
Rose Thompson
83df3dfe83 Fixed the zifencei bug (part of issue 405). 2024-01-15 16:02:37 -06:00
Rose Thompson
edc56c669e Fixed bug 546. non-leaf non-zero PBMT bit raise page fault. 2024-01-05 17:10:14 -06:00
David Harris
680a014876 Finished LSU tlbcontrol coverage tests 2024-01-02 10:16:20 -08:00
David Harris
f4ee05e1ea Coverage improvements 2024-01-01 08:31:09 -08:00
David Harris
e5ac2d5ef0 Modified align fsm to make coverage easier 2024-01-01 08:21:31 -08:00
Rose Thompson
730efefc41 Cleanup. 2023-12-29 16:18:30 -06:00
Rose Thompson
6a787981c2 Restored cache store delay hazard. 2023-12-29 16:10:27 -06:00
Rose Thompson
0264a17f77 Reverted dtim to use store delay stall, but only (load after store). 2023-12-29 16:06:30 -06:00
Rose Thompson
f59fa5089d Merge branch 'main' of https://github.com/openhwgroup/cvw 2023-12-29 15:13:18 -06:00
Rose Thompson
8030b7d100 Added partial code for uncached amo operations. 
Minor fix for Makefile so coverage tests build.
 2023-12-29 15:07:20 -06:00
Rose Thompson
52dad4f130 cbo.zero works for uncached memory now! 2023-12-29 11:11:06 -06:00
David Harris
e8df856fdb Renamed CMOp to CMOpM in mmu and cache 2023-12-25 05:57:41 -08:00
David Harris
29f57958a9 Fixed WALLY-lrsc in ImperasDV by setting reservation set size to native word size and adjusting imperas.ic lr_sc_grain=8 to match 2023-12-14 15:32:36 -08:00
Rose Thompson
9f4c32d49c Merge branch 'main' of github.com:ross144/cvw 2023-12-13 20:32:59 -06:00
Rose Thompson
b69a5b59cd DTIM works without the store delay stall. Still a bit of work remaining. The DTIM needs cleanup. 
The cache needs a bit of clean up and the chapter needs updates.
The controller needs to be updated to remove the store delay hazard for cmo instructions.
 2023-12-13 20:32:14 -06:00
David Harris
6c017141c5 Renamed HADE to ADUE for Svadu 2023-12-13 11:49:04 -08:00
Rose Thompson
13bb5d845b On the way to solving the store delay hazard. 2023-12-13 10:39:01 -06:00
Rose Thompson
1ebc7aa95a Optimized align. 2023-12-03 16:43:55 -06:00
Rose Thompson
d29b2b95f7 Additional cleanup. 2023-11-28 23:28:50 -06:00
Rose Thompson
4149ae6c11 More cleanup. 2023-11-28 23:05:47 -06:00
Rose Thompson
143c6ca4d1 Simplification to alignment. 2023-11-28 22:28:11 -06:00
Rose Thompson
a69a70ba7f Removed unused hardware from alignment. 2023-11-28 19:54:25 -06:00
Rose Thompson
865ebf8b9b cclsm cleanup. 2023-11-28 19:41:46 -06:00
Rose Thompson
f4e77e9669 Clean up. 2023-11-28 14:21:37 -06:00
Rose Thompson
df85428041 More optimizations for cclsm. 2023-11-28 14:19:30 -06:00
Rose Thompson
4d4790ecf9 Optimizations to cclsm. 2023-11-28 14:18:06 -06:00
Rose Thompson
195def5808 Extended the abhcacheinterface to zero a cacheline's worth of uncached memory on cbo.zero. 2023-11-27 21:24:30 -06:00
Rose Thompson
beb95dd592 Modified the pmachecker to correctly check the permissions for cmo instructions. 
However this isn't fully tested.
 2023-11-27 17:44:11 -06:00
Rose Thompson
337903d8dd More cache simplifications. 2023-11-27 14:59:42 -06:00
David Harris
1f57df7f8b Fixed reference to deleted atomic signal in cache 2023-11-23 20:29:10 -08:00
David Harris
d3ce683e06 Removed other unused signals from Verilog 2023-11-20 23:37:56 -08:00
David Harris
f89fd8a7fe removed unused cache signals 2023-11-20 23:16:35 -08:00
David Harris
acd8a63628 Merge pull request #489 from ross144/main 
fixes issue #487
 2023-11-18 19:22:33 -08:00
Rose Thompson
8cbd3de413 Fixed Zicclsm bug. Misalignment and spill detection were not masked by access type. Therefore a page table walk which always aligned could have had an IEUAdrM misaligned which erroneously caused a shift in the read data. 2023-11-18 19:01:39 -06:00
David Harris
eef39bd495 Fixed typo in lsu parameter 2023-11-15 08:30:48 -08:00
David Harris
817ddbc7c5 Adjusted LSU misaligned buffer to fix synthesis warning 2023-11-15 08:19:50 -08:00
Rose Thompson
a6995af91c Fixed bug in uncore updates which broke SDC. 2023-11-13 16:15:23 -06:00
Rose Thompson
707b0c557c Cleanup and optimization of Zicclsm. 2023-11-13 14:28:22 -06:00
Rose Thompson
cc7a0b211a Cleanup. 2023-11-13 12:35:11 -06:00
Rose Thompson
c8cca8dfb8 Simplification. 2023-11-10 18:39:36 -06:00
Rose Thompson
c0e02ae190 Found another bug in the RTL's Zicclsm alignment. 2023-11-10 18:26:55 -06:00
Rose Thompson
02ab9fe99c Fixed all the bugs associated with the signature and the store side of misaligned access. Load misaligned is still causing some issues. 2023-11-10 17:58:42 -06:00
Rose Thompson
84d86b1994 Fixed spill bugs in the aligner. 2023-11-10 17:18:45 -06:00
Rose Thompson
b74bfbeefd Merge branch 'main' into Zicclsm 2023-11-10 16:15:32 -06:00
Rose Thompson
9abd26aad9 Fixed bug which broke the non Zicclsm configs. 2023-11-10 16:08:04 -06:00
David Harris
1f2899de14 Modified rams to take USE_SRAM rather than P to facilitate synthesis 2023-11-03 05:44:13 -07:00
Rose Thompson
0a4ed5515b Merge branch 'main' into Zicclsm 2023-11-02 12:55:51 -05:00
Rose Thompson
13333d3e82 Finally the d$ spill works. At least until the next bug. Definitely needs a lot of cleanup. 2023-11-01 14:25:18 -05:00
Rose Thompson
5660eff57d Working through issues with the psill logic. 2023-10-31 18:50:13 -05:00
Rose Thompson
f13b67b869 Preemptively fixed the bytemask bug before testing. 2023-10-30 15:47:46 -05:00
Rose Thompson
b5763e11e8 rv32gc now also works with the alignment module. Still not tested with misligned access. 2023-10-30 15:30:09 -05:00
Rose Thompson
9cd2e47783 Aligner is integrated and enabled in rv64gc and passes the regression test; however, there are no new tests. 2023-10-30 14:54:58 -05:00
Rose Thompson
569e3dc906 Finally lints cleanly. 2023-10-30 14:00:49 -05:00
Rose Thompson
dce3c85105 Progress. 2023-10-27 16:31:22 -05:00
Rose Thompson
747f453bb5 Passes lint with some exceptions. Still need to add misaligned store support. 2023-10-27 14:41:42 -05:00
Rose Thompson
36ca64c567 At least have the aligner integrated, but not tested. 2023-10-27 13:55:16 -05:00
Rose Thompson
657409aec5 Addec ZICCLSM to config files and started on lsu instance. 2023-10-27 13:07:23 -05:00
Rose Thompson
6041bf20b3 The misaligned load alignment lints. 2023-10-27 11:41:49 -05:00
Rose Thompson
834c0df697 Added file. 2023-10-27 09:49:44 -05:00
Rose Thompson
449abef823 Progress on misaligned load/stores. 2023-10-27 09:35:44 -05:00
Rose Thompson
12763b7297 begin implemenation of Zicclsm. 2023-10-26 11:51:20 -05:00
David Harris
3bb7539429 Fixed warnings of signed conversion and for Design Compiler 2023-10-24 14:01:43 -07:00
David Harris
d526d28804 Added MENVCFG.HADE bit and updated SVADU to depend on this bit 2023-10-04 09:34:28 -07:00
David Harris
bd6eef2a51 Initial implementation of SVNAPOT and SVPBMT does not break regression 2023-08-25 18:33:08 -07:00
Ross Thompson
4eeba9bed9 Added cbom test to custom. Needs to be moved to wally-riscv-arch-tests. 2023-08-18 15:59:39 -05:00
Ross Thompson
0eac74ac7b Initial CMO implementation. Just adds control signals into the L1 caches. 2023-08-14 15:43:12 -05:00
Ross Thompson
7a196d3fa7 Cache cleanup. 2023-07-31 14:12:53 -05:00
Ross Thompson
15dc76310e Fixed lint errors for issue #368. Does not fix simulation errors. We made a design decision a long time ago to not support DTIM on the rv32gc config because LLEN was greater than XLEN. 2023-07-26 15:08:01 -05:00
Ross Thompson
f895898d22 Improved the critical path even more. The Arty A7 works upto 19Mhz easily. Testing out 22Mhz now. 2023-07-21 16:31:26 -05:00
Ross Thompson
d04d2afed2 Modified the LSU/IFU and caches to improve critical path. Arty A7 went from 15 to 17Mhz. I believe we can push all the way to 20+Mhz with relatively little effort. Along the way I'm fixing up the scripts build the linux images for the flash card. 2023-07-21 13:06:27 -05:00
David Harris
afe66d0ee4 Added prefetch instructions; sent cbo instructions to LSU 2023-07-02 10:55:35 -07:00
Ross Thompson
85567841eb Merge branch 'testbench-params2' 2023-06-15 15:31:13 -05:00
Ross Thompson
009d8966e9 Got the srams parameterized correctly now. 2023-06-15 13:42:24 -05:00
Ross Thompson
b8a243827b Found a whole bunch of files still using the old `define configurations. 2023-06-15 13:09:07 -05:00
Harshini Srinath
15928c5d7b Update swbytemask.sv 
Program clean up
 2023-06-12 13:37:35 -07:00
Harshini Srinath
f3a7d9030c Update subwordwrite.sv 
Program clean up
 2023-06-12 13:35:27 -07:00
Harshini Srinath
f1f21f0896 Update subwordread.sv 
Program clean up
 2023-06-12 13:31:54 -07:00