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219 Commits

Author SHA1 Message Date
Rose Thompson
3d0f9ce4f3 Cleaned up comments about pc reset. 2023-12-13 13:06:33 -06:00
Rose Thompson
c98c0dd3e0 Removed unnecessary pc reset logic from ifu and btb. 2023-12-13 13:05:10 -06:00
Rose Thompson
13bb5d845b On the way to solving the store delay hazard. 2023-12-13 10:39:01 -06:00
Rose Thompson
195def5808 Extended the abhcacheinterface to zero a cacheline's worth of uncached memory on cbo.zero. 2023-11-27 21:24:30 -06:00
Rose Thompson
beb95dd592 Modified the pmachecker to correctly check the permissions for cmo instructions. 
However this isn't fully tested.
 2023-11-27 17:44:11 -06:00
David Harris
d3ce683e06 Removed other unused signals from Verilog 2023-11-20 23:37:56 -08:00
David Harris
f89fd8a7fe removed unused cache signals 2023-11-20 23:16:35 -08:00
David Harris
8cb433cb66 Commented IROM preloading 2023-11-19 19:33:57 -08:00
David Harris
1f2899de14 Modified rams to take USE_SRAM rather than P to facilitate synthesis 2023-11-03 05:44:13 -07:00
David Harris
dd072c80f2 Updated testbenches to capture InstrM because it may be optimized out of IFU 2023-11-03 05:24:15 -07:00
David Harris
402538e13c Temporary fix of InstrM to prevent testbench hanging 2023-11-03 04:59:44 -07:00
David Harris
09aebbf252 Fixed regression error of watchdog timeout when PCM is optimized out of the IFU 2023-11-03 04:38:27 -07:00
David Harris
680fb3f30b Conditionally instantiate hardware in ifu 2023-10-30 20:55:00 -07:00
David Harris
afabc52b61 Gated InstrOrigM and PCMReg when not needed 2023-10-30 20:05:37 -07:00
David Harris
90a178e31e Made 2-bit AdrReg conditional on being needed 2023-10-30 19:13:43 -07:00
David Harris
f6a7f707bd Fixed test cases for medeleg issue 444. Also added a COMPRESSED_SUPPORTED parameter true when C or Zca is supported, and use this to get compressed hardware such as the spill logic and the +2 adder. 2023-10-30 09:56:17 -07:00
David Harris
734bf021d7 Merge branch 'main' of https://github.com/openhwgroup/cvw into dev 2023-10-26 19:02:05 -07:00
David Harris
3bb7539429 Fixed warnings of signed conversion and for Design Compiler 2023-10-24 14:01:43 -07:00
Rose Thompson
694ec18934 Added support for branch counters when there is no branch predictor. 2023-10-23 15:32:03 -05:00
Rose Thompson
1611d5ec3c Fixed issue 250. instruction classification was not correct for jalr ra (non zero). 2023-10-23 15:30:43 -05:00
David Harris
28752303be Added ZCA/ZCF/ZCD/ZCB support. Doesn't break regression, but not tested. Need to get tests for Zcb. Draft tests are in riscv-arch-test but not yet committed there 2023-10-04 12:28:12 -07:00
David Harris
19a6bbb01b UpdateDA cleanup: don't assert UpdateDA when there is no SVADU 2023-10-04 09:57:13 -07:00
David Harris
d526d28804 Added MENVCFG.HADE bit and updated SVADU to depend on this bit 2023-10-04 09:34:28 -07:00
Ross Thompson
f863cbf366 Actually fixed non-power of 2 issue with RAS. 
Added RAS swapping to branch predictor scripts and configurations.
 2023-09-27 12:25:05 -05:00
Ross Thompson
aeacb481aa Fixed sutble RAS bug when the stack size was not a power of 2. 2023-09-27 12:00:47 -05:00
David Harris
8f12c6f9a1 initial spill logic improvement 2023-09-03 04:21:13 -07:00
David Harris
bd6eef2a51 Initial implementation of SVNAPOT and SVPBMT does not break regression 2023-08-25 18:33:08 -07:00
Ross Thompson
0eac74ac7b Initial CMO implementation. Just adds control signals into the L1 caches. 2023-08-14 15:43:12 -05:00
Ross Thompson
7a196d3fa7 Cache cleanup. 2023-07-31 14:12:53 -05:00
Ross Thompson
d04d2afed2 Modified the LSU/IFU and caches to improve critical path. Arty A7 went from 15 to 17Mhz. I believe we can push all the way to 20+Mhz with relatively little effort. Along the way I'm fixing up the scripts build the linux images for the flash card. 2023-07-21 13:06:27 -05:00
Ross Thompson
538efaf771 Optimized critial path in ifu's spill logic. 2023-07-19 14:13:46 -05:00
Ross Thompson
b756b248b4 Wow. The newest version of Vivado does not like the enums as parameters. 
The solution is simple.  I changed the type to logic [31:0] and defined macros for the branch predictor types as 32 bit integers.
 2023-07-18 15:07:10 -05:00
Ross Thompson
85567841eb Merge branch 'testbench-params2' 2023-06-15 15:31:13 -05:00
Ross Thompson
75b5c23edd Actually removed old `define configuration file for rv64gc. There were a lot of dangling problems. 2023-06-15 14:05:44 -05:00
Ross Thompson
009d8966e9 Got the srams parameterized correctly now. 2023-06-15 13:42:24 -05:00
Ross Thompson
b8a243827b Found a whole bunch of files still using the old `define configurations. 2023-06-15 13:09:07 -05:00
Harshini Srinath
3593762cfa Merge branch 'main' into main 2023-06-14 11:52:45 -07:00
harshini
8570b2f332 deleting CodeAligner file 2023-06-13 17:41:37 -07:00
Harshini Srinath
9d0fc0a138 Update spill.sv 
Program clean up
 2023-06-12 12:50:11 -07:00
Harshini Srinath
19e8acff70 Update irom.sv 
Program clean up
 2023-06-12 12:44:09 -07:00
Harshini Srinath
a5561c2cf6 Update ifu.sv 
Program clean up
 2023-06-12 12:38:52 -07:00
Harshini Srinath
b5c655b1c3 Update decompress.sv 
Program clean up
 2023-06-12 12:27:55 -07:00
Harshini Srinath
d0ede93dc1 Update CodeAligner.py 
Program clean up
 2023-06-12 12:25:47 -07:00
David Harris
df96900aa1 Added named support for Zicntr and Zihpm 2023-06-09 09:35:51 -07:00
Ross Thompson
a963f0af3a Updated source code to be compatible with verilator 5.011 for lint only. 2023-05-31 10:44:23 -05:00
Ross Thompson
04d0fd94f0 Merge branch 'param-lim-merge' 2023-05-26 16:25:35 -05:00
Ross Thompson
1315a0bf4a Got the branch predictor parameterized using Lim's method. Also had to add a global enum included in both cvw.sv and the configs which defines the branch predictor types. This should be synthesizable, but I'll need to double check. 2023-05-26 16:00:14 -05:00
Ross Thompson
fcb1c63f5f Partial parameterization into mmu. 2023-05-24 16:12:41 -05:00
Ross Thompson
052bc95966 More parameterization. Copied Lim. Still no slow down. 2023-05-24 14:49:22 -05:00
Ross Thompson
b91b54589e Updated a large number of the source files to use parameters rather than `defines. Based on Lim's work. So far there is no simulation slow down. 2023-05-24 14:05:44 -05:00
Ross Thompson
6d2e3070a5 Merged changes. 2023-05-24 13:15:52 -05:00
Ross Thompson
80aa0888f3 Updated headers to local branch history predictors. 2023-05-24 12:52:42 -05:00
Ross Thompson
69a9bf7055 Adds local history predictor. 
Fixes performance counters, but not coremark.
 2023-05-23 18:53:46 -05:00
Ross Thompson
d545a2ec74 Partially working local history repair. 2023-05-11 14:56:26 -05:00
Ross Thompson
3a98fb8680 Baseline localhistory with speculative repair built. 2023-05-05 15:23:45 -05:00
Ross Thompson
42517bae6f Fixed bug in local history predictor. 2023-05-04 16:54:41 -05:00
Ross Thompson
ee1e380fad Almost working ahead pipelined local history predictor. 2023-05-04 16:17:31 -05:00
Ross Thompson
8235042ba2 Maybe I finally have the ahead pipelined local history predictor working. 2023-05-04 14:11:34 -05:00
Ross Thompson
060d40853a Ahead pipelining is not yet working. :( 2023-05-03 17:41:38 -05:00
Ross Thompson
8b0791b6b5 I think ahead pipelining is working for local history. 2023-05-03 12:52:32 -05:00
Ross Thompson
414c79b923 Updated configs for local branch history `defines. 2023-05-02 11:11:04 -05:00
Ross Thompson
08b237b878 Added comment explaining the difference between global history and local history basic implementations. 2023-05-02 11:01:46 -05:00
Ross Thompson
0904a9b97f Swapped the m and k parameters for local history predictor. 2023-05-02 10:52:41 -05:00
Ross Thompson
4eff75449a Maybe have the baseline local history predictor working. 2023-05-01 15:45:27 -05:00
Ross Thompson
5777b90407 Might actually have a correct implementation of local history branch prediction. 2023-04-24 13:05:28 -05:00
Ross Thompson
e81445be5d Fixed the local branch predictor so that it at least compiles. 2023-04-24 11:06:53 -05:00
Limnanthes Serafini
b3976daccd More cleanup 2023-04-13 21:34:50 -07:00
Limnanthes Serafini
034c289a36 Misc typo and indent fixing. 2023-04-13 16:54:15 -07:00
Kevin Thomas
f7838b869b Merge branch 'main' of https://github.com/openhwgroup/cvw 2023-04-08 22:56:20 -05:00
David Harris
2f4074b9c2 Improved RAS predictor coverage by eliminating unreachable StallM term 2023-04-07 21:37:12 -07:00
David Harris
7ad05d9a42 Removed redundant stall signal to get spill coverage 2023-04-06 14:07:50 -07:00
Kevin Thomas
4d30aff198 Formating white space 2023-04-05 15:30:55 -05:00
Kevin Thomas
0c80067d45 Minor change with the IFU in the decompress module, in the compressed instruction truth table. 
The truth table is already fully covered, removed redundant last case checking
 2023-04-05 10:27:52 -05:00
Sydney Riley
55655157ae expanded ifu coverage including 4 added directed tests and 1 exclusion, expanded fpu coverage including 6 directed tests and 2 multiline exclusions. 2023-04-02 23:51:34 -07:00
Ross Thompson
366a96a0fc Possible fix for issue 148. 
I found the problem. We use a Committed(F/M) signal to indicate the IFU or LSU has an ongoing cache or bus transaction and should not be interrupted. At the time of the mret, the IFU is fetching uncacheable invalid instructions asserting CommittedF. As the IFU finishes the request it unstalls the pipeline but continues to assert CommittedF. (This is not necessary for the IFU). In the same cycle the LSU d cache misses. Because CommittedF is blocking the interrupt the d cache submits a cache line fetch to the EBU.

I am thinking out loud here. At it's core the Committed(F/M) ensure memory operations are atomic and caches don't get into inconsistent states. Once the memory operation is completed the LSU/IFU removes the stall but continues to hold Committed(F/M) because the memory operation has completed and it would be wrong to allow an interrupt to occur with a completed load/store. However this is not true of the IFU. If we lower CommittedF once the operation is complete then this problem is solved. The interrupt won't be masked and the LSU will flush the d cache miss.

This requires a minor change in the cachebusfsm and cachefsm. I will report back after I've confirmed this works.
 2023-03-28 14:47:08 -05:00
Ross Thompson
46b1bca4fc Fixed all tap/space issue in RTL. 2023-03-24 17:32:25 -05:00
David Harris
e03a533775 Select original compressed or uncompressed instruction for MTVAL on illegal instruction fault 2023-03-22 06:29:30 -07:00
David Harris
a1eccf37dc Fix Issue 145 2023-03-22 04:33:14 -07:00
Ross Thompson
3cae6ca90f Updated NextAdr to NextSet. 2023-03-13 14:54:13 -05:00
Ross Thompson
ada099c58b Changes BTA to BPBTA. 2023-03-12 14:36:46 -05:00
Ross Thompson
a5523400ae Replaced DCACHE parameter with READ_ONLY_CACHE as the name was confusing in chapter 10. 2023-03-12 13:21:22 -05:00
Ross Thompson
a6b851a672 Renamed signals to be consistent with textbook. 2023-03-06 18:29:31 -06:00
Ross Thompson
31fcc0daf7 Renamed PCFSpill to PCSpillF. 2023-03-06 17:50:57 -06:00
Ross Thompson
473ed2b475 Renamed InstrFirstHalf to InstrFirstHalfF. 2023-03-06 17:48:57 -06:00
Ross Thompson
0cb5369351 Renamed BTB misprediction to BTA. 2023-03-03 00:18:34 -06:00
Ross Thompson
aabb454d1c Added the i and d cache cycle counters. 2023-03-02 23:54:56 -06:00
Ross Thompson
b98e007a53 Cleaned up branch predictor performance counters. 2023-03-01 17:05:42 -06:00
Ross Thompson
90b2f0a652 Set bp to use instruction class prediction by default. 2023-03-01 11:52:42 -06:00
Ross Thompson
dea6b643a6 Branch predictor cleanup. 
I think Ch 10 is now done except for BTB performance analysis and the section on running benchmarks and collecting data.
 2023-03-01 11:24:24 -06:00
Ross Thompson
03a6679ba0 More btb cleanup. 2023-03-01 10:47:00 -06:00
Ross Thompson
554e7d0973 Minor fix to btb. 2023-03-01 10:45:40 -06:00
Ross Thompson
a6917d07f3 Name cleanup. 2023-02-28 17:48:58 -06:00
Ross Thompson
4c0e7f297a Found the performance bug with the branch predictor btb power saving update. 2023-02-28 15:57:34 -06:00
Ross Thompson
2ebe600f54 Name changes to reflect diagrams. 2023-02-28 15:37:25 -06:00
Ross Thompson
be4823f7dd Undid the btb update as it reduces performance. 2023-02-28 15:21:56 -06:00
Ross Thompson
9dd3379744 This icpred and btb changes are causing a performance issue. 2023-02-27 20:00:50 -06:00
Ross Thompson
544abe2819 Modified the BTB to save power by not updating when the prediction is unchanged. 2023-02-27 17:37:29 -06:00
Ross Thompson
bc5aecf948 Merge branch 'main' of https://github.com/openhwgroup/cvw 2023-02-27 09:48:03 -06:00
Ross Thompson
318189e5e6 Signal name changes. 2023-02-27 00:39:19 -06:00
Ross Thompson
c89812b2d4 Branch predictor cleanup. 2023-02-26 21:28:36 -06:00