Rose Thompson
77d47e531f
Merge branch 'main' into lrufixes
2024-11-13 10:34:21 -06:00
Rose Thompson
2fe73f8174
Replaced double | and & with single. We were having issues with these verilator giving a warning about the parameter widths not matching. However the warning is not occuring anymore.
2024-11-13 00:02:51 -06:00
Rose Thompson
8993432928
Resolved issue with questa not liking the TEST +arg as a generate.
2024-11-12 23:57:30 -06:00
Rose Thompson
ef7072b7c2
Merge branch 'main' into lrufixes
2024-11-12 17:57:28 -06:00
Rose Thompson
8659d6efdb
Resolved all CacheSim.py vs Wally mismaches.
2024-11-12 17:24:06 -06:00
Rose Thompson
57fbd35484
Fixed lint errors in loggers.sv with Kaitlin.
2024-11-12 15:03:30 -06:00
Rose Thompson
b7b7c79726
CBO.FLUSH was not clearing the valid bit if the cacheline was clean.
2024-11-12 14:16:55 -06:00
Rose Thompson
5cc1fd4a85
Getting closer. Oly the wally64priv tests mismatch between the cachesim and wally.
2024-11-12 12:08:14 -06:00
Rose Thompson
8a4868ac57
Resolved a bug in the cache but there are still mismatches with the cache simulator.
2024-11-12 11:35:29 -06:00
Rose Thompson
0cf7b2e45a
Progress on fixing the cache simulator to support cbo instructions.
2024-11-11 16:37:17 -06:00
Rose Thompson
8fb1673ab3
Updated email address authorship for my files.
2024-10-15 10:27:53 -05:00
Huda-10xe
b77df83b59
Adding DUT signals to the tracer for VM Coverage
2024-10-07 03:52:36 -07:00
Huda-10xe
24f97fa696
Adding DUT signals to the tracer for VM Coverage
2024-10-07 03:49:43 -07:00
Huda-10xe
0817c69152
Adding priv coverage to ISACOV
2024-10-07 03:44:35 -07:00
Rose Thompson
1345a0f315
Merge branch 'main' of https://github.com/openhwgroup/cvw
2024-09-24 10:13:50 -05:00
David Harris
6157023d16
Merge branch 'main' of https://github.com/openhwgroup/cvw into dev
2024-08-29 15:07:18 -07:00
David Harris
0e9e7d0a49
Fixed wallyTracer floating-point register FLEN
2024-08-29 11:11:19 -07:00
Rose Thompson
6ad2c2e7a6
Merge pull request #935 from davidharrishmc/dev
...
Added lockstep support for RV32. Not all wally privileged tests pass…
2024-08-29 10:45:17 -07:00
David Harris
26f3c2a607
Added lockstep support for RV32. Not all wally privileged tests pass yet
2024-08-29 10:44:37 -07:00
Rose Thompson
113d71f1a0
More name updates.
2024-08-21 10:51:24 -07:00
Rose Thompson
f603d21826
Updated my name in multiple locations.
2024-08-21 10:50:39 -07:00
David Harris
010038ec32
Depricate conditional generation based on A_SUPPORTED, which is now computed from ZALRSC_SUPPORTED and ZAAMO_SUPPORTED
2024-08-08 05:27:35 -07:00
David Harris
fa98ae8c30
Depricate conditional generation based on A_SUPPORTED, which is now computed from ZALRSC_SUPPORTED and ZAAMO_SUPPORTED
2024-08-08 05:27:35 -07:00
Rose Thompson
7164841f83
Added padding into the hw rvvi format.
2024-08-06 18:34:46 -05:00
Rose Thompson
ce61429bdf
Fixed the reset bug in wallyTracer.
2024-07-24 13:32:46 -05:00
Rose Thompson
5a6e32576d
Fixed the reset bug in wallyTracer.
2024-07-24 13:32:46 -05:00
Rose Thompson
d0a5b278b7
Factored out the rvvi testbench code into rvvitbwrapper.
2024-07-24 13:10:57 -05:00
Rose Thompson
13db14db6b
Factored out the rvvi testbench code into rvvitbwrapper.
2024-07-24 13:10:57 -05:00
David Harris
f30cc46ec5
Disable misaligned accesses in imperas configuration and check misaligned support requires D$
2024-07-21 08:26:07 -07:00
David Harris
f5f8a6c50c
Disable misaligned accesses in imperas configuration and check misaligned support requires D$
2024-07-21 08:26:07 -07:00
David Harris
e72c8b8e09
Watchdog timeout on buildroot boot is a halting criteria
2024-07-02 14:22:51 -07:00
David Harris
38b0c10f9b
Updated wallyTracer to be compatible with VCS
2024-07-02 04:47:53 -07:00
Ross Thompson
5e5ca0809f
Removed more *** from lsu and updated assertions for dtim.
2024-06-19 10:52:51 -07:00
David Harris
4a4bbdfc43
More code cleanup
2024-06-14 09:50:07 -07:00
David Harris
53477b2c85
Code cleanup
2024-06-14 07:08:17 -07:00
David Harris
b1c9450b4a
Code cleanup: RAM, fdivsqrt
2024-06-14 03:35:05 -07:00
David Harris
312c9c9f55
Updated logger to new IClass signal name
2024-06-12 07:24:05 -07:00
Rose Thompson
9a42aab971
Merge pull request #804 from jordancarlin/dev
...
Eliminate more logical operators and replace with bitwise operators
2024-05-16 15:45:18 -05:00
Jordan Carlin
1d8ffee20c
Certain Zcb instructions are dependent on other extensions, not the entire extension
2024-05-15 19:16:43 -07:00
Jordan Carlin
ef778da98d
Eliminate more logical operators and replace with bitwise
2024-05-15 10:50:23 -07:00
Jordan Carlin
4ffce9a752
Switch riscvassertions to use bitwise operators instead of logical operators per Wally style guide
2024-05-15 09:23:24 -07:00
Jordan Carlin
291d1e62d5
M implies Zmmul
2024-05-14 19:38:34 -07:00
Jordan Carlin
4a72922087
update config to derive MISA from macros
...
- Remove C_SUPPORTED and update decompress unit based on Zc* extensions
- Derive A_SUPPORTED from A subextensions
- Derive B_SUPPORTED from B subextensions
- Derive C_SUPPORTED from C subextensions
2024-05-14 06:49:18 -07:00
David Harris
77137f0f60
ZAAMO and ZALRSC implemented but not tested
2024-05-07 16:45:49 -07:00
David Harris
9b22275438
Removed unused signals from WallyTracer
2024-04-30 08:54:28 -07:00
David Harris
a1876b1e7c
script cleanup
2024-04-20 17:22:31 -07:00
David Harris
ac9a21873d
Pass TEST to testbench with +TEST=<name> rather than -G TEST=<name> so that we don't have to recompile for every new test
2024-04-06 10:34:21 -07:00
Rose Thompson
081cf5be55
Fixed the CacheHit logger bug.
2024-03-28 13:40:01 -05:00
Kunlin Han
22b59138f0
Remove all #delay from non-testbench.
2024-03-16 11:20:32 -07:00
Kunlin Han
8c67a76912
Remove all #delay from non-testbench.
2024-03-13 10:31:40 -07:00
