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774 Commits

Author SHA1 Message Date
Noah Boorstin
d0a137ce0c neat verilog thing 2021-04-18 17:48:51 -04:00
Noah Boorstin
5902637632 buildroot: sim is now running! 
yes it only gets through 5 instructions right now. Yes that's my fault.
 2021-04-17 14:44:32 -04:00
Noah Boorstin
541fb22dc9 start to add buildroot testbench 
This still uses testbench-busybear.sv
I think it might be time to finally rename nearly 'busybear' thing to 'linux'
 2021-04-16 23:27:29 -04:00
Jarred Allen
3868a82932 dcache lints 2021-04-15 21:13:56 -04:00
Jarred Allen
32cfbc6926 Enable linting of blocks not yet in the hierarchy 2021-04-15 21:13:40 -04:00
bbracker
11cf251378 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-04-15 21:09:27 -04:00
bbracker
195cead01c working GPIO interrupt demo 2021-04-15 21:09:15 -04:00
Domenico Ottolia
b1cd107a00 Add tests for scause and ucause 2021-04-15 19:41:25 -04:00
Domenico Ottolia
a149f2f3d8 Add support for vectored interrupts 2021-04-15 19:13:42 -04:00
Domenico Ottolia
70b79ca301 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-04-15 16:57:27 -04:00
Domenico Ottolia
8c4cfa5f69 Add 32 bit privileged tests 2021-04-15 16:55:39 -04:00
Teo Ene
a9c6d357d8 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-04-15 15:29:09 -05:00
Teo Ene
7a40c27b59 Quick fix to ahblite missing default statement done in class :) 2021-04-15 15:29:04 -05:00
Thomas Fleming
e8770e3eac Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 
Conflicts:
	wally-pipelined/src/mmu/priority_encoder.sv
 2021-04-15 16:20:43 -04:00
Thomas Fleming
e838f0bb3d Change priority encoder to avoid extra assignment 2021-04-15 16:17:35 -04:00
Thomas Fleming
2c4682c4be Connect tlb and icache properly 2021-04-15 14:48:39 -04:00
Teo Ene
cefc8ea22b Temporary change to mmu/priority_encoder.sv 
Necessary to get synth working
Original HDL is still there, just commented out
 2021-04-15 13:37:12 -05:00
Katherine Parry
0bdd3efdd5 integraded the FMA into the FPU 2021-04-15 18:28:00 +00:00
Jarred Allen
7b4b1a31ef Merge branch 'main' into cache 2021-04-15 13:47:19 -04:00
Ross Thompson
534e3eaac8 Merge branch 'bpfixes' into main 2021-04-15 09:06:21 -05:00
Shreya Sanghai
75caa65df1 Cherry Pick merge of Shreya's localhistory predictor changes into main. 
fixed minor bugs in localHistory
 2021-04-15 09:04:36 -05:00
ShreyaSanghai
80fbd66113 added localHistoryPredictor 2021-04-15 08:58:22 -05:00
Shreya Sanghai
3696bf4f2c fixed bugs in global history to read latest GHRE 
Cherry pick Shreya's commits into main branch.
 2021-04-15 08:55:22 -05:00
bbracker
76f50d7a69 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-04-15 09:06:03 -04:00
bbracker
da22308e60 csri lint improvement 2021-04-15 09:05:53 -04:00
Jarred Allen
4d58f673b2 Add a comment to explain a detail 2021-04-14 23:14:59 -04:00
Thomas Fleming
d281ecd067 Remove imem from testbenches 2021-04-14 20:20:34 -04:00
Jarred Allen
c32fe09056 More icache bugfixes 2021-04-14 19:03:33 -04:00
Jarred Allen
757b64e487 Merge branch 'main' into cache 
Conflicts:
	wally-pipelined/src/cache/dmapped.sv
	wally-pipelined/src/cache/line.sv
	wally-pipelined/src/ifu/icache.sv
 2021-04-14 18:24:32 -04:00
bbracker
ccff1e6c99 rv64 interrupt servicing 2021-04-14 10:19:42 -04:00
Noah Boorstin
3e0ed5a2b1 busybear: use (slightly) less terrible verilog 2021-04-14 00:18:44 -04:00
Noah Boorstin
18a4d5fc8d busybear testbench updates 
start speculative checking on CSR* satp, *
add some slight delays in some CSR checkings to make them deterministic

I realize this verilog is incredibly un-idiomatic. But I still don't
know of anything better. If you figure it out, please let me know
 2021-04-14 00:00:27 -04:00
Thomas Fleming
bb2d433971 Fix mmu lint errors 2021-04-13 19:19:58 -04:00
Thomas Fleming
a545dcb9ae Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-04-13 17:15:10 -04:00
Katherine Parry
e075dc2d13 Various bugs fixed in FMA 2021-04-13 18:27:13 +00:00
Thomas Fleming
ae888b5705 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 
Conflicts:
	wally-pipelined/src/ebu/pagetablewalker.sv
 2021-04-13 13:42:03 -04:00
Thomas Fleming
f0c926cf68 Move InstrPageFault to fetch stage 2021-04-13 13:39:22 -04:00
Thomas Fleming
08a84048b6 Add lru algorithm to TLB 2021-04-13 13:37:24 -04:00
Teo Ene
0bffac2c74 Various code syntax changes to bring HDL to a synthesizable level 2021-04-13 11:27:12 -05:00
Jarred Allen
95ad9a93a4 Merge branch 'main' into cache 2021-04-13 01:10:03 -04:00
Jarred Allen
357aed75ee A few more cache fixes 2021-04-13 01:07:40 -04:00
Ross Thompson
cb52820249 Fixed minor bug in muldiv which corrects the lint error. 2021-04-09 10:56:31 -05:00
ushakya22
c8c2d63163 Latest IE tests with timer interupts 2021-04-08 17:53:39 -04:00
Jarred Allen
6ce4d44ae1 Merge from branch 'main' 2021-04-08 17:19:34 -04:00
Ross Thompson
75b97f1422 Created special test for driving the instruction spill error. 
The extact problem occurs when a 4 byte instruction startles two cache blocks (or without a cache two ahbi words) and the code jumps to a cache block other than the next cache block. Consider the following sample of code.

0000000000000080 <test_spill>:
  80:	42a9                	li	t0,10
  82:	0001                	nop
  84:	0001                	nop
  86:	0001                	nop
  88:	02bd                	addi	t0,t0,15
  8a:	00628e33          	add	t3,t0,t1
  8e:	01ce8963          	beq	t4,t3,a0 <match>

0000000000000092 <failure>:
  92:	557d                	li	a0,-1
  94:	8082                	ret
  96:	00000013          	nop
  9a:	00000013          	nop
  9e:	0001                	nop

00000000000000a0 <match>:
  a0:	1ffd                	addi	t6,t6,-1
  a2:	fc0f9fe3          	bnez	t6,80 <test_spill>
  a6:	4501                	li	a0,0
  a8:	8082                	ret

Instructions 0x88, 0x8a and 0x8e are read incorrectly.  However once the branch predictor begins to correctly predict the beq at 0x8e the instrution at 0xa0 is loaded incorrectly as the 2 upper bytes of 0x8e and the two bytes of 0x92.  This amalgamation causes c.addi at 0xa0 to do something else and the loop never terminates.

The button of wavefile wave.do shows the exact problem in the 'icache'.
 2021-04-08 15:05:08 -05:00
bbracker
0c85b1c201 integrated peripheral testing into existing workflow 2021-04-08 15:31:39 -04:00
bbracker
37bca569ff Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-04-08 14:28:25 -04:00
bbracker
c8c87bd0d8 merge testbench 2021-04-08 14:28:01 -04:00
Katherine Parry
6e4a22ec4b Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-04-08 18:06:51 +00:00
David Harris
5b262159cd Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-04-08 14:04:09 -04:00
David Harris
2a7dd37441 restored testbench-imperas.sv 2021-04-08 14:04:01 -04:00
Katherine Parry
21efd0cad9 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-04-08 18:03:57 +00:00
Katherine Parry
08f45eb076 fixed FPU lint warnings 2021-04-08 18:03:21 +00:00
Katherine Parry
ebf4915440 fixed FPU lint warnings 2021-04-08 17:55:25 +00:00
ushakya22
6dc982285c Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-04-08 13:55:23 -04:00
ushakya22
0dfeb76f10 Updates to WALLY-IE tests 2021-04-08 13:54:42 -04:00
David Harris
2203e64b65 merge conflict resolution 2021-04-08 13:53:56 -04:00
David Harris
aabebdb59f fixed sim-wally-32ic 2021-04-08 13:40:16 -04:00
Noah Boorstin
5f1cd43033 try to remove git-lfs stuff 2021-04-08 13:23:11 -04:00
Domenico Ottolia
d6949b5b81 Update privileged testgen & helper script 2021-04-08 05:14:07 -04:00
Domenico Ottolia
1bdfac6a77 Cause an Illegal Instruction Exception when attempting to write readonly CSRs 2021-04-08 05:12:54 -04:00
Thomas Fleming
bd310a55af Refactor TLB into multiple files 2021-04-08 03:24:10 -04:00
Thomas Fleming
b3795cef2e Provide attribution link for priority encoder 2021-04-08 03:05:06 -04:00
Thomas Fleming
e807f5d771 Implement support for superpages 2021-04-08 02:44:59 -04:00
Ross Thompson
7f12c7af90 Switch to use RV64IC for the benchmarks. 
Still not working correctly with the icache.

instr
addr   correct   got
 2021-04-07 19:12:43 -05:00
ushakya22
7888eacc3f MIE privilege tests with working timer interupt 2021-04-07 04:09:09 -04:00
Domenico Ottolia
9b82fbff5a Add privileged tests to testbench 2021-04-07 02:22:08 -04:00
Domenico Ottolia
bbdd4e1467 Add passing mtval and mepc tests 2021-04-07 02:21:05 -04:00
Ross Thompson
d901cfc848 Merge branch 'icache_bp_bug' into tests 
Not sure this merge is right.
 2021-04-06 21:46:40 -05:00
Ross Thompson
a5dc175ab2 Merge remote-tracking branch 'refs/remotes/origin/tests' into tests 2021-04-06 21:20:55 -05:00
Ross Thompson
0a20e33971 Steps to getting branch predictor benchmarks running. 2021-04-06 21:20:51 -05:00
Jarred Allen
4da2688c40 Fix another bug in icache 2021-04-06 17:47:00 -04:00
Jarred Allen
ecb2bc8163 Fix another bug in icache 2021-04-06 12:48:42 -04:00
Noah Boorstin
c820910b29 add busybear boot files with git-lfs 2021-04-05 19:38:43 -04:00
Noah Boorstin
ce22a1de04 busybear: reenable 'ruthless' CSR checking 2021-04-05 12:53:30 -04:00
bbracker
80a67dc906 declare memread signal 2021-04-05 08:13:01 -04:00
bbracker
eca92041e9 PLIC claim reg side effects now check for memread signal 2021-04-05 08:03:14 -04:00
bbracker
8f4da826fb plic subword access compliance 2021-04-04 23:10:33 -04:00
Katherine Parry
f41b5a2d38 Added missing files in FPU 2021-04-04 18:09:13 +00:00
bbracker
ce7b2314ef Yee hoo first draft of PLIC plus self-checking tests 2021-04-04 06:40:53 -04:00
Thomas Fleming
5946b860ca Comment out fpu from hart until module exists 2021-04-03 22:34:11 -04:00
Thomas Fleming
8f31e00f6a Merge branch 'mmu' into main 
Conflicts:
	wally-pipelined/src/wally/wallypipelinedhart.sv
 2021-04-03 22:12:52 -04:00
Thomas Fleming
ac89947e98 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-04-03 22:09:50 -04:00
Noah Boorstin
2f503ee6b9 busybear: temporary stop after 800k instrs 2021-04-03 21:37:57 -04:00
Thomas Fleming
e04ad8f304 Fix extraneous page fault stall 2021-04-03 21:28:24 -04:00
Jarred Allen
4ebc991a65 Fix bug in icache 2021-04-03 18:10:54 -04:00
Katherine Parry
08b31f7b2a Integrated FPU 2021-04-03 20:52:26 +00:00
Ross Thompson
a743acd1fd Partial fix to the integer divide stall issue. 2021-04-02 15:32:15 -05:00
James E. Stine
e38e7aff8e Minor cleanup 2021-04-02 08:20:44 -05:00
James E. Stine
82cd900b65 Put back imperas testbench until figure out why m_supported is running for rv64ic 2021-04-02 08:19:25 -05:00
James E. Stine
9026357350 Added some updates to divider - still not working all the time. Still a bug with signals within muldiv - specificaly MultDivE being modified during Execute stage. Seems to be triggered by ahblite signal. 2021-04-02 06:27:37 -05:00
Thomas Fleming
14cf331265 Merge branch 'main' into mmu 2021-04-01 16:29:39 -04:00
Thomas Fleming
06032936bd Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-04-01 16:24:06 -04:00
Thomas Fleming
3f3d8f414d Merge branch 'mmu' of github.com:davidharrishmc/riscv-wally into mmu 2021-04-01 16:23:19 -04:00
Thomas Fleming
f9bf2fbc01 Implement sfence.vma and fix tlb writing 2021-04-01 15:55:05 -04:00
Jarred Allen
8dc57a7706 Begin changes to direct-mapped cache 2021-04-01 13:55:21 -04:00
Shreya Sanghai
bf3f4ff5b2 fixed minor bugs in localHistory 2021-04-01 13:40:08 -04:00
James E. Stine
59dee5580c Fixed some divide -still bug in AHB causing InstStall to deassert and next instruction to get into divide unit. Hope to fix soon. Divide seems to work if given enough time. 2021-04-01 12:30:37 -05:00
ShreyaSanghai
e33007e30e added localHistoryPredictor 2021-04-01 22:22:40 +05:30
Shreya Sanghai
65e9747752 fixed bugs in global history to read latest GHRE 2021-03-31 21:56:14 -04:00
Teo Ene
6aed8eaea1 Updated MISA in coremark_bare config file 2021-03-31 20:39:02 -05:00
Noah Boorstin
4e62c7d5f5 busybear: temporarially stop checking CSRs 2021-03-31 14:14:32 -04:00
Noah Boorstin
679daeedf5 busybear: clean up questa warnings 2021-03-31 14:04:57 -04:00
Noah Boorstin
ddc56d8cd7 busybear: clean up questa warnings 2021-03-31 14:02:15 -04:00
Ross Thompson
f1107c5d7b Corrected a number of bugs in the branch predictor. 
Added performance counters to individually track
branches; jumps, jump register, jal, and jalr; return.
jump and jump register are special cases of jal and jalr.
Similarlly return is a special case of jalr.
Also added counters to track if the branch direction was wrong,
btb target wrong, or the ras target was wrong.
Finally added one more counter to track if the BP incorrectly predicts
a non-cfi instruction.
 2021-03-31 11:54:02 -05:00
Ross Thompson
1e83810450 Merge of main with the new icache and the branch predictor. I believe there is a bug in the icache with unaligned memory access. The second part of the access is incorrectly relying on the PCF being the address of the next two bytes of the instruction. However this is not always the case as the branch predictor can get the wrong target address. The icache needs to generate the +2 address internally. 2021-03-30 23:18:20 -05:00
Thomas Fleming
9388a9f28a Disable 'always-on' virtual memory 2021-03-30 22:49:47 -04:00
Thomas Fleming
e35020b7dc Extend lint-wally to lint both rv32 and rv64 2021-03-30 22:42:28 -04:00
Thomas Fleming
e3d548d452 Merge remote-tracking branch 'origin/main' into main 
Bring icache and MMU code together

Conflicts:
	wally-pipelined/src/ifu/ifu.sv
	wally-pipelined/testbench/testbench-imperas.sv
 2021-03-30 22:24:47 -04:00
Thomas Fleming
4b2765f8e2 Complete basic page table walker 2021-03-30 22:19:27 -04:00
Thomas Fleming
7f7cc73dd3 Update virtual memory tests and move to separate folder 2021-03-30 22:18:29 -04:00
Domenico Ottolia
d0a78b15b7 Add one more test to WALLY-CAUSE, and update privileged testgen 2021-03-30 19:44:58 -04:00
Domenico Ottolia
8c7e247b58 Add mcause tests to testbench 2021-03-30 17:17:59 -04:00
Domenico Ottolia
ae7868b166 Update privileged tests generator 2021-03-30 16:58:46 -04:00
Domenico Ottolia
47648dc721 Add all working mcause tests 2021-03-30 16:55:12 -04:00
ushakya22
ba01d57767 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-03-30 15:25:07 -04:00
ushakya22
2b99a7657a privilege tests 2021-03-30 15:23:47 -04:00
Ross Thompson
a3925505bf fixed some bugs with the RAS. 2021-03-30 13:57:40 -05:00
Jarred Allen
6cda818f09 Merge branch 'cache2' into cache 
Conflicts:
	wally-pipelined/testbench/testbench-imperas.sv
 2021-03-30 13:32:33 -04:00
Jarred Allen
dd0b3fde59 Comment out failing tests 2021-03-30 13:07:26 -04:00
Jarred Allen
335178a1d3 Merge branch 'cache' into main 2021-03-30 12:56:19 -04:00
Jarred Allen
85164c7a87 Merge branch 'main' into cache 
Conflicts:
	wally-pipelined/regression/wave-dos/ahb-waves.do
	wally-pipelined/src/ifu/ifu.sv
	wally-pipelined/testbench/testbench-busybear.sv
	wally-pipelined/testbench/testbench-imperas.sv
 2021-03-30 12:55:01 -04:00
David Harris
9f0a58e193 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-03-26 13:04:52 -04:00
David Harris
aa0d0d50d8 Added fp test to testbench 2021-03-26 13:03:23 -04:00
Noah Boorstin
606295db2f Merge branch 'main' into cache 
Conflicts:
	wally-pipelined/testbench/testbench-busybear.sv
 2021-03-26 12:26:30 -04:00
Shreya Sanghai
edaf89e3d1 Merge branch 'PPA' into main 
Conflicts:
	wally-pipelined/testbench/testbench-privileged.sv
 2021-03-25 20:35:21 -04:00
Shreya Sanghai
d3e914f64b removed minor bugs 2021-03-25 20:29:50 -04:00
Jarred Allen
c8a88757ab Fix error when reading an instruction that crosses a line boundary 2021-03-25 18:47:23 -04:00
ShreyaSanghai
da4086db79 Removed PCW and InstrW from ifu 2021-03-26 01:53:19 +05:30
Jarred Allen
7338ddf853 Remove old icache 2021-03-25 15:46:35 -04:00
Jarred Allen
fa6e6f1724 Works for misaligned instructions not on line boundaries 2021-03-25 15:42:17 -04:00
Noah Boorstin
ee3a53de7a regression: use busybear batch instead 2021-03-25 15:34:10 -04:00
Domenico Ottolia
9e9fe5e9d3 More bug fixes for privileged tests 2021-03-25 15:05:55 -04:00
Jarred Allen
73d4dd8c15 Begin work on compressed instructions 2021-03-25 14:43:10 -04:00
Noah Boorstin
9eb1786fb1 busybear: quick fix to mem reading 
also stop ignoring mcause at the start
 2021-03-25 14:29:11 -04:00
Brett Mathis
aedc96cd04 FPU Pipeline completed - can begin integration 2021-03-25 13:29:03 -05:00
Domenico Ottolia
fb00d0f209 Fix bugs with privileged tests 2021-03-25 14:06:05 -04:00
Noah Boorstin
ed37e933e5 busybear: stop NOPing out atomics 
and bump regression to check for 800k instrs, up from 200k
 2021-03-25 13:29:56 -04:00
Jarred Allen
feabcf2d50 Make cache output NOP after a reset 2021-03-25 13:18:30 -04:00
David Harris
dea2ec280e testgen-PIPELINE python startup 2021-03-25 13:12:18 -04:00
Shriya Nadgauda
e55a245948 adding PIPELINE tests 2021-03-25 13:07:25 -04:00
Jarred Allen
fdecd6c56c Clean up some stuff 2021-03-25 13:04:54 -04:00
Jarred Allen
15e786da0b Working for all of rv64i now, but not compressed instructions 2021-03-25 13:02:26 -04:00
Jarred Allen
e8e4e1bee2 rv64i linear control flow now working 2021-03-25 13:02:26 -04:00
Jarred Allen
08f4ce4438 More progress on icache controller 2021-03-25 13:01:11 -04:00
Jarred Allen
fff70bccbc Begin rewrite of icache module to use a direct-mapped scheme 2021-03-25 13:01:10 -04:00
Jarred Allen
5a86225e1c Fix bug in cache line 2021-03-25 12:59:30 -04:00
Jarred Allen
abedaf62a8 Output NOP instead of BAD when reset 2021-03-25 12:42:48 -04:00
Jarred Allen
2f5d854f87 Merge branch 'main' into cache 
Conflicts:
	wally-pipelined/src/uncore/dtim.sv
 2021-03-25 12:10:26 -04:00
Teo Ene
7c3963547d Config file for ppa experiments 2021-03-25 10:23:21 -05:00
David Harris
1158b3aa73 Added PPA README 2021-03-25 11:21:31 -04:00
Thomas Fleming
89a2fe5741 Finish finite state machines for page table walker 2021-03-25 02:48:40 -04:00
Thomas Fleming
4f01aae844 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-03-25 02:35:21 -04:00
bbracker
d52c71086a added 1 tick delay to dtim flops 2021-03-25 02:23:30 -04:00
bbracker
ca392225df added 1 tick delay on tim reads 2021-03-25 02:15:28 -04:00
Jarred Allen
9cbdb44728 Merge branch 'main' into cache 
Conflicts:
	wally-pipelined/src/ifu/ifu.sv
 2021-03-25 00:51:12 -04:00
bbracker
6edb055f26 instrfault direspecting stalls bugfix 2021-03-25 00:44:35 -04:00
bbracker
5327dcfcc8 instrfaults not respecting stalls bugfix 2021-03-25 00:16:26 -04:00
bbracker
a8b7d7a248 upgraded gpio bus interface 2021-03-25 00:15:02 -04:00
bbracker
3e656fc035 future work comment about suspicious-looking verilog in csri.sv 2021-03-25 00:10:44 -04:00
Thomas Fleming
f2604797fb Add all PMP addr registers 2021-03-24 21:58:33 -04:00
Teo Ene
1e691e120b Fix typo from last commit 2021-03-24 17:09:58 -05:00
Teo Ene
9f44eb36ef Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-03-24 17:04:48 -05:00
Teo Ene
6a7b69ff2d Updated coremark_bare testbench for IM 2021-03-24 17:04:43 -05:00
Katherine Parry
123e63b440 fixed various bugs in the FMA 2021-03-24 21:51:17 +00:00
Teo Ene
07f7df82e3 Added BPTYPE to coremark_bare config 2021-03-24 16:38:29 -05:00
Ross Thompson
cdb7d15709 Fixed bugs with the csr interacting with StallW. StallW is required to pervent updating a csr. Now have a working branch predictor and performance counters to track the number of commited branches and mispredictions. 2021-03-24 15:56:55 -05:00
Ross Thompson
a768c0406c Updated the function radix to have a new name FunctionName and it now pervents false transisions from the current function name when the PCD is flushed. 2021-03-24 13:03:43 -05:00
Domenico Ottolia
3909158619 re-organize privileged tests to be in rv64p to rv32p folders 2021-03-24 13:51:25 -04:00
Jarred Allen
0776127c75 Give some cache mem inputs a better name 2021-03-24 12:31:50 -04:00
Jarred Allen
abf9f3b3cb Fix compile errors from const not actually being constant (why does Verilog do this) 2021-03-24 00:58:56 -04:00
Ross Thompson
ace39940b4 Fixed RAS errors. Still some room for improvement with the BTB and RAS. 2021-03-23 23:00:44 -05:00
Jarred Allen
1f01a12be9 Merge branch 'main' into cache 2021-03-23 23:35:36 -04:00
Ross Thompson
72d25d4443 Fixed a bunch of bugs with the RAS. 2021-03-23 21:49:16 -05:00
Katherine Parry
fb78dedae2 fixed various bugs in the FMA 2021-03-24 01:35:32 +00:00
Ross Thompson
c318606f05 Fixed the valid bit issue. Now the branch predictor is actually predicting instructions. 2021-03-23 20:20:23 -05:00
Ross Thompson
9d5c351340 fixed issue with BTB's valid bit not updating. There is still a problem is valid not ocurring in the correct clock cycle. 2021-03-23 20:06:45 -05:00
Ross Thompson
dee5d16850 fixed a whole bunch of bugs with the branch predictor. Still an issue with how PCNextF is not updated because the CPU is stalled. 2021-03-23 16:53:48 -05:00
Jarred Allen
ebd2c60b74 Begin work on direct-mapped cache 2021-03-23 17:03:02 -04:00
Teo Ene
8556c07261 Added BOOTTIM to InstrAccessFaultF calculation in uncore/imem 2021-03-23 15:21:13 -05:00
Ross Thompson
4836e8fe2c Simulation definitely shows the branch predictor counters and branch predictor don't work. :( 2021-03-23 14:04:58 -05:00
Ross Thompson
c7e34bd4a0 added a whole bunch of interseting test code for branches which does not work. 2021-03-23 13:54:59 -05:00
Ross Thompson
c4f7c65210 updated the branch predictor config. 2021-03-23 13:54:59 -05:00
Ross Thompson
9909bdd4d5 Added first benchmark. 2021-03-23 13:54:59 -05:00
Ross Thompson
cebb2bc44d Temporary exe2memfile0.pl script to support starting addresses of 0. 2021-03-23 13:54:59 -05:00
Ross Thompson
e6aef66853 Broken commit. Trying to get exe2memfile.pl to work correctly with non 0x8000_0000 starting addresses. 2021-03-23 13:54:59 -05:00
Noah Boorstin
355961f834 busybear: more progress 2021-03-23 14:49:30 -04:00
Shreya Sanghai
09b90557f7 PC counts branch instructions 2021-03-23 14:25:51 -04:00
Jarred Allen
c16605a105 Remove deleted signal from waves 2021-03-23 14:17:17 -04:00
Noah Boorstin
0dae5401f3 busybear: more progress moving from instrf to instrrawd 2021-03-23 14:06:21 -04:00
Noah Boorstin
7fb2ebec50 busybear: ignore illegal instruction when starting 2021-03-23 13:28:56 -04:00
Jarred Allen
789c189260 Another tweak to regression-wally.py comments 2021-03-23 00:18:38 -04:00
Jarred Allen
34cc9b4aeb Document some internal signals 2021-03-23 00:10:35 -04:00
Jarred Allen
e4ebb4e31e Add comments explaining icache inputs 2021-03-23 00:07:39 -04:00
Jarred Allen
2c4eda2ba3 Slight change to regression-wally.py comments 2021-03-23 00:02:40 -04:00
Jarred Allen
c47a80213e Small commit to see if new hook tests non-main branch 2021-03-22 23:57:01 -04:00
Noah Boorstin
3c131bb2bd start migrating busybear over to InstrRawD/PCD 
this breaks busybear for now
 2021-03-22 23:45:04 -04:00
Noah Boorstin
1592332d41 Merge branch 'main' into cache 2021-03-22 23:28:30 -04:00
Noah Boorstin
43d23e3d9b busybear: add better warning on illegal instruction 
...also it seems that mret is being picked up as an illegal instruction??
 2021-03-22 18:24:35 -04:00
Noah Boorstin
4160bf50b0 busybear: temporarially force rf[5] correct after failure to read CSR 2021-03-22 18:12:41 -04:00
Noah Boorstin
4be19421c4 busybear: allow overwriting read values 2021-03-22 17:28:44 -04:00
Noah Boorstin
b4166e9fd0 busybear: finally get the right error 2021-03-22 16:52:22 -04:00
bbracker
c3a6d6bf42 added delays to uart AHB signals 2021-03-22 15:40:29 -04:00
Jarred Allen
307e33bc7e Remove DelaySideD since it isn't needed 2021-03-22 15:13:23 -04:00
Jarred Allen
99fa8beef3 Update icache interface 2021-03-22 15:04:46 -04:00
Noah Boorstin
7350b9f18f busybear: comment out some debug printing 2021-03-22 14:54:05 -04:00
Jarred Allen
507d8ed120 Merge branch 'main' into cache 2021-03-22 14:50:22 -04:00
Noah Boorstin
c4fb51fad1 regression: expect 200k instead of 100k busybear instrs 
and a minor busybear bugfix
 2021-03-22 14:47:52 -04:00
Jarred Allen
2269879459 Merge branch 'main' into cache 2021-03-22 13:47:48 -04:00
bbracker
eea7e2e47e first pass at PLIC interface 2021-03-22 10:14:21 -04:00
Katherine Parry
9af0ad815c fixed various bugs in the FMA 2021-03-21 22:53:04 +00:00
Jarred Allen
bab0e3b90f Change busybear testbench to reflect new location of InstrF 2021-03-20 18:20:27 -04:00
Jarred Allen
e32291bcc2 Put Imperas testbench back 2021-03-20 18:19:51 -04:00
Jarred Allen
066dc2caac Fix bug with PC incrementing 2021-03-20 18:06:03 -04:00
Jarred Allen
e531a1b5ee Merge branch 'main' into cache 2021-03-20 17:56:25 -04:00
Jarred Allen
665c244ba1 Fix another bug in the icache (why so many of them?) 2021-03-20 17:54:40 -04:00
Jarred Allen
43a8cb0354 Revert "Change flop to listen to StallF" 
This reverts commit f069b759be.
 2021-03-20 17:34:19 -04:00
Jarred Allen
639a718312 Fix conflicts in ahb-waves that snuck through manual merging 2021-03-20 17:16:50 -04:00
Jarred Allen
f069b759be Change flop to listen to StallF 2021-03-20 17:04:13 -04:00
Katherine Parry
fd381e60d7 messy FMA rewrite using section 7.5.4 in The Handbook of Floating-Point Arithmetic 2021-03-20 02:05:16 +00:00
Jarred Allen
50c961bbe4 Merge changes from main 2021-03-18 18:58:10 -04:00
Jarred Allen
bf2fbf49ee Add icache's read request to ahb wavs 2021-03-18 18:52:03 -04:00
bbracker
df51d9908d AHB bugfixes and sim waveview refactoring 2021-03-18 18:25:12 -04:00
bbracker
11ba96f2e3 maybe AHB works now 2021-03-18 17:47:00 -04:00
Shreya Sanghai
804407eab7 fixed minor bugs in testbench 2021-03-18 17:37:10 -04:00
Shreya Sanghai
dfc86539cc Merge branch 'gshare' into main 
Conflicts:
	wally-pipelined/regression/wave.do
 2021-03-18 17:25:48 -04:00
Ross Thompson
9386e6a524 Switched to gshare from global history. 
Fixed a few minor bugs.
 2021-03-18 16:05:59 -05:00
Ross Thompson
181a28e875 Fixed minor bug with the size of gshare. 2021-03-18 16:00:09 -05:00
Shreya Sanghai
f35d3b39c8 removed unnecesary PC registers in ifu 2021-03-18 16:31:21 -04:00
Thomas Fleming
859d242d81 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-03-18 14:36:42 -04:00
Thomas Fleming
062c4d40da Connect tlb, pagetablewalker, and memory 2021-03-18 14:35:46 -04:00
Thomas Fleming
f04e554e35 Improve page table creation in python file 2021-03-18 14:27:09 -04:00
Noah Boorstin
847bf0b9a6 change ifndef to generate/if 2021-03-18 12:50:19 -04:00
Noah Boorstin
fa1407f6e3 everyone gets a bootram 2021-03-18 12:35:37 -04:00
Noah Boorstin
a226e24ed3 busybear: update memory map, add GPIO 2021-03-18 12:17:35 -04:00
Teo Ene
0ff785549e Switched coremark to RV64IM 2021-03-17 22:39:56 -05:00
Teo Ene
db164462ed adapted coremark bare testbench to new dtim RAM HDL 2021-03-17 16:59:02 -05:00
Jarred Allen
e39ead0460 Merge branch 'main' into cache 
Conflicts:
	wally-pipelined/testbench/testbench-imperas.sv
 2021-03-17 16:40:52 -04:00
Teo Ene
29634f1475 Temporarily reverted my last few commits 2021-03-17 15:16:01 -05:00
Teo Ene
e6661ea26a fix to last commit 2021-03-17 15:07:02 -05:00
Teo Ene
90946d61c5 fix to last commit 2021-03-17 15:02:15 -05:00
Teo Ene
083a24c06b addition to last commit 2021-03-17 14:52:31 -05:00
Teo Ene
ca901513c8 Added Ross's addr lab stuff to coremark stuff 2021-03-17 14:50:54 -05:00
Elizabeth Hedenberg
bccd37d778 fixing coremark branch prediction 2021-03-17 15:15:55 -04:00
Elizabeth Hedenberg
74ebe0bef2 replicating coremark changes into coremark bare 2021-03-17 14:36:34 -04:00
Elizabeth Hedenberg
a3b2ffb2c9 Merge branch '3_3_2021' into main 
Making sure coremark works with spring break changes
 2021-03-17 14:11:37 -04:00
Ross Thompson
7bc95ba073 Fixed issue with sim-wally-batch. Are people still using this script? 2021-03-17 11:17:52 -05:00
Ross Thompson
0e2352a6de Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-03-17 11:07:57 -05:00
Ross Thompson
31ad619a21 Added possibly working OSU test bench as a precursor to running a bp benchmark. 
Fixed a few bugs with the function radix.
 2021-03-17 11:06:32 -05:00
Domenico Ottolia
150faf8dd8 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-03-16 23:27:09 -04:00