Ross Thompson
|
ad485fe591
|
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
|
2022-08-25 09:03:34 -05:00 |
|
Ross Thompson
|
701324eeb8
|
Updated ila signals.
Improve fpga wave config.
added back in the fpga preload.
|
2022-08-25 09:03:29 -05:00 |
|
David Harris
|
ae0702d129
|
Renamed DCache to Cache in busdp/busfsm signal interface
|
2022-08-25 06:21:22 -07:00 |
|
David Harris
|
3500286803
|
Cleanup typos
|
2022-08-25 04:32:19 -07:00 |
|
David Harris
|
db5c941d6f
|
Minor name cleanups
|
2022-08-25 04:28:25 -07:00 |
|
David Harris
|
1206b388c7
|
Replaced dtim with rom-based IROM in IFU. Moved cache control signals out of DTIM and IROM
|
2022-08-25 04:06:27 -07:00 |
|
David Harris
|
f7209627c2
|
removed simpleram and modified dtim to use bram1p1rw
|
2022-08-25 03:39:57 -07:00 |
|
David Harris
|
562be633ab
|
Stripped write capaibilty out of rom_ahb
|
2022-08-24 17:23:08 -07:00 |
|
David Harris
|
a131e1f17a
|
Added ROM module and moved memories into generic/mem
|
2022-08-24 17:03:22 -07:00 |
|
David Harris
|
6785644fb8
|
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
|
2022-08-24 16:30:28 -07:00 |
|
David Harris
|
b21b91234b
|
Ram cleanup
|
2022-08-24 16:30:25 -07:00 |
|
Ross Thompson
|
769af32f2a
|
Renamed RAM to UNCORE_RAM.
|
2022-08-24 18:09:07 -05:00 |
|
Ross Thompson
|
fc22e807e2
|
Merged testbench-fpga into testbench.
Modified SDC to simplify LimitTimers. LimitTimers needs to be 0 for implmementation and 1 for simulation.
|
2022-08-24 17:52:25 -05:00 |
|
Ross Thompson
|
d23b309e0d
|
Fixed lint errors with bram wrapper.
|
2022-08-24 13:19:23 -05:00 |
|
Ross Thompson
|
51adf6cba9
|
Modified the lsu/ifu memory configurations.
|
2022-08-24 12:35:15 -05:00 |
|
David Harris
|
bcb52acfba
|
bram synthesis test
|
2022-08-23 19:34:45 -07:00 |
|
Ross Thompson
|
e4cbb43c67
|
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
|
2022-08-23 18:52:15 -05:00 |
|
Ross Thompson
|
642dc170d7
|
Found small bug in busfsm which was issuing 1 extra memory read after each cache line fetch. Does not appear to have translated to an extra read out of ahblite.
|
2022-08-23 18:51:11 -05:00 |
|
David Harris
|
5eebd521c5
|
Fixed FPU-IEU forwarding stall
|
2022-08-23 14:14:41 -07:00 |
|
David Harris
|
d72068d582
|
Only stall FPU to IEU on convert instructions with dependencies
|
2022-08-23 12:57:18 -07:00 |
|
David Harris
|
05aa18fe14
|
Cleaned up fcvt selection control to IEU and FPUIllegalInst signals
|
2022-08-23 12:17:19 -07:00 |
|
David Harris
|
d19fc99bf0
|
Simplify IEU-FP datapath
|
2022-08-23 11:16:36 -07:00 |
|
David Harris
|
f72d07adce
|
Improved illegal instruction checking in FPU
|
2022-08-23 11:08:02 -07:00 |
|
David Harris
|
c61dba6192
|
Fixed LSU typos
|
2022-08-23 10:23:08 -07:00 |
|
David Harris
|
2a1bd53663
|
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
|
2022-08-23 10:14:59 -07:00 |
|
David Harris
|
029aecabf7
|
typo in srtfsm
|
2022-08-23 10:14:54 -07:00 |
|
Katherine Parry
|
fe0c6afe58
|
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally
|
2022-08-23 16:36:32 +00:00 |
|
Katherine Parry
|
4e33ead413
|
renamed rounding bits to L,G,R,S and fixed lint warning
|
2022-08-23 16:36:20 +00:00 |
|
Ross Thompson
|
20ba6fd19c
|
Reversed order of supported sized in adrdecs.
|
2022-08-23 11:14:53 -05:00 |
|
Ross Thompson
|
5efec3b1f3
|
Replaced FPU data replicaiton on WriteData bus with 0 extention.
|
2022-08-23 10:46:03 -05:00 |
|
Ross Thompson
|
aa5cbab0d8
|
Replaced LSU data replication with 0 extention.
|
2022-08-23 10:43:47 -05:00 |
|
Ross Thompson
|
3b07584403
|
Updated the names of the *WriteDataM inside the LSU to more meaningful names.
Moved the FWriteDataMux so that the bus and dtim both get fpu stores.
Modified the PMA to disallow double sized reads when XLEN=32.
|
2022-08-23 10:34:39 -05:00 |
|
David Harris
|
e714b75888
|
LSU minor edits
|
2022-08-23 07:35:47 -07:00 |
|
David Harris
|
3c91df95d9
|
Named HTRANS states in busfsm
|
2022-08-22 13:56:46 -07:00 |
|
David Harris
|
6cfbf95d98
|
Renamed signals for LSU - FPU interface
|
2022-08-22 13:47:56 -07:00 |
|
David Harris
|
c789b5789c
|
renamed GrantData to LSUGrant
|
2022-08-22 13:47:19 -07:00 |
|
David Harris
|
0e489443f2
|
Finished FPU-LSU interface cleanup
|
2022-08-22 13:43:04 -07:00 |
|
David Harris
|
ea153e0aad
|
Removed FStore2 and simplified HPTW
|
2022-08-22 13:29:54 -07:00 |
|
David Harris
|
8444eca57c
|
Simplified FPU-LSU interface to skip IEU
|
2022-08-22 13:29:20 -07:00 |
|
David Harris
|
774cddf33c
|
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
|
2022-08-22 13:28:54 -07:00 |
|
David Harris
|
d556adde16
|
Simplified FPU-LSU interface to skip IEU
|
2022-08-22 13:28:51 -07:00 |
|
Katherine Parry
|
a9be193a35
|
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally
|
2022-08-22 17:16:25 +00:00 |
|
Katherine Parry
|
36be692c0b
|
sqrt passes - lint warnings remain
|
2022-08-22 17:16:12 +00:00 |
|
David Harris
|
2e20b3ed72
|
Removed 2-cycle FPU-IEU latency stall
|
2022-08-22 16:14:15 +00:00 |
|
David Harris
|
bdfc49f847
|
moved CSA to generic
|
2022-08-22 08:41:23 +00:00 |
|
David Harris
|
f10793e85d
|
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally
|
2022-08-22 08:28:31 +00:00 |
|
David Harris
|
f6f09db4fb
|
Commented out unused comparators
|
2022-08-22 08:28:28 +00:00 |
|
Ross Thompson
|
dbbb3ff1d1
|
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
|
2022-08-21 16:03:11 -05:00 |
|
Ross Thompson
|
ebe4339953
|
Updated fpga test bench.
Solved read delay cache bug. Introduced during cache optimizations.
|
2022-08-21 15:59:54 -05:00 |
|
Ross Thompson
|
85dbec5969
|
Hmm. Found a bug with the cache's changes from the summer. Cannot return data to CPU at the same time as a write to cache's SRAM and also start another memory operation.
|
2022-08-21 15:28:29 -05:00 |
|
Ross Thompson
|
f3f0f12904
|
Removed logic from Verilog wrapper.
|
2022-08-21 14:07:43 -05:00 |
|
Katherine Parry
|
a191603a1a
|
fixed -1 issue in division
|
2022-08-20 00:53:45 +00:00 |
|
Ross Thompson
|
2ba390adf4
|
Possible reduction of ignorerequest.
|
2022-08-19 18:07:44 -05:00 |
|
Ross Thompson
|
517c0f6c35
|
Changed signal names.
|
2022-08-17 16:12:04 -05:00 |
|
Ross Thompson
|
f6e5746e59
|
Better name for LSUBusWriteCrit. Changed to SelLSUBusWord.
|
2022-08-17 16:09:20 -05:00 |
|
Ross Thompson
|
299aefb76a
|
Removed old code from interlockfsm.
|
2022-08-17 12:52:56 -05:00 |
|
Katherine Parry
|
9549c23f45
|
sqrt tests in regression uncommented and pass
|
2022-08-07 23:38:10 +00:00 |
|
Katherine Parry
|
cb0c1b7488
|
radix-2 1 copy passes testfloat
|
2022-08-06 22:54:05 +00:00 |
|
Katherine Parry
|
de6ae471bc
|
fixed fsw problem and removed 2 bit shift from shift correction
|
2022-08-03 22:16:51 +00:00 |
|
David Harris
|
e70b28f7f6
|
FMA cleanup
|
2022-08-02 07:42:32 -07:00 |
|
David Harris
|
2b932c4b80
|
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
|
2022-08-02 07:34:12 -07:00 |
|
David Harris
|
887e4c73fb
|
Moved InvA to sign block; simplified fmaexpadd coding
|
2022-08-02 07:34:09 -07:00 |
|
Ross Thompson
|
413a9bf58b
|
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
|
2022-08-01 22:09:11 -05:00 |
|
Ross Thompson
|
57fcf0ef79
|
Fixed fstore2 in cache?
|
2022-08-01 22:04:44 -05:00 |
|
David Harris
|
06c4f18cd1
|
merged lza back into main
|
2022-08-01 19:45:21 -07:00 |
|
David Harris
|
8147f75399
|
Fixed fmaadd to work with new LZA
|
2022-08-01 19:40:55 -07:00 |
|
Ross Thompson
|
797d9e3610
|
Replaced swbytemask with swbytemaskword (1 liner). Credit to David Harris.
|
2022-08-01 21:12:25 -05:00 |
|
Ross Thompson
|
3cd8404917
|
Replaced LOGWPL with LOGBWPL (Bus words per line) and LOGCWPL (cache words per line). Replaced with wordlen/8 bytemask.
|
2022-08-01 21:08:14 -05:00 |
|
Ross Thompson
|
3612db2d70
|
pulled swbbytemask out of subword write.
|
2022-08-01 20:48:45 -05:00 |
|
David Harris
|
7e4b04ff64
|
Parameterized fmalza
|
2022-08-01 16:18:02 -07:00 |
|
David Harris
|
94fa7a00e7
|
Completed LZA simplificaiton
|
2022-08-01 16:13:16 -07:00 |
|
David Harris
|
3b937b73fd
|
lza cleanup
|
2022-08-01 16:01:02 -07:00 |
|
David Harris
|
b614f165fb
|
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
|
2022-08-01 15:47:58 -07:00 |
|
David Harris
|
91597bba87
|
lza cleanup
|
2022-08-01 15:47:03 -07:00 |
|
David Harris
|
f56b26ec40
|
lza cleanup
|
2022-08-01 15:43:48 -07:00 |
|
David Harris
|
c3e9719c99
|
lza cleanup
|
2022-08-01 15:40:12 -07:00 |
|
David Harris
|
d6b5e7a6ef
|
lza cleanup
|
2022-08-01 15:37:09 -07:00 |
|
Katherine Parry
|
8ff3a693af
|
regression passes fpu tests
|
2022-08-01 19:56:25 +00:00 |
|
Katherine Parry
|
9c68f85822
|
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally
|
2022-08-01 19:55:50 +00:00 |
|
David Harris
|
2869d67e50
|
more lza cleanup
|
2022-08-01 12:34:00 -07:00 |
|
David Harris
|
b34d2065c3
|
LZA cleanup
|
2022-08-01 12:30:42 -07:00 |
|
David Harris
|
99462049e7
|
LZA refactoring switched to Pp1, Gm1, Km1
|
2022-08-01 12:20:23 -07:00 |
|
David Harris
|
3c08aabcd3
|
LZA refactoring
|
2022-08-01 11:36:21 -07:00 |
|
Katherine Parry
|
eddf6e9ee1
|
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally
|
2022-08-01 18:35:07 +00:00 |
|
David Harris
|
7f9b601467
|
fmalza edits to match textbook
|
2022-08-01 18:23:39 +00:00 |
|
David Harris
|
257107f908
|
Partitioned fma into separate files
|
2022-08-01 18:07:38 +00:00 |
|
Ross Thompson
|
1ee613ae6c
|
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
|
2022-07-31 12:48:51 -05:00 |
|
Katherine Parry
|
1bd6351e1f
|
re-added FStore2 in Cache
|
2022-07-29 22:54:49 +00:00 |
|
David Harris
|
93d7d7179e
|
Added parity and stop bit tests to UART
|
2022-07-28 04:35:51 +00:00 |
|
Ross Thompson
|
40e7cda84a
|
Don't use this commit yet. Untested.
|
2022-07-24 15:40:52 -05:00 |
|
Ross Thompson
|
719b00e338
|
Overlapped read fetch line end with eviction write line start. I'm a bit concerned this is not well tested.
|
2022-07-24 01:20:29 -05:00 |
|
Ross Thompson
|
69d520a7eb
|
Removed replay from the config files.
|
2022-07-24 00:34:11 -05:00 |
|
Ross Thompson
|
cd68896637
|
Merged evict dirty clear with flush write back.
|
2022-07-24 00:22:43 -05:00 |
|
Ross Thompson
|
8193946996
|
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
|
2022-07-23 08:41:59 -05:00 |
|
Ross Thompson
|
05484c4c05
|
signal name cleanup.
|
2022-07-22 23:36:27 -05:00 |
|
Ross Thompson
|
27e32980ad
|
cache cleanup after removing replay on cpubusy.
|
2022-07-22 23:30:25 -05:00 |
|
Ross Thompson
|
17ae1a1b1b
|
cache fsm cleanup after removal of replay.
|
2022-07-22 23:25:09 -05:00 |
|
Ross Thompson
|
abc79c6c8e
|
Possible improvement to cache which removes the cpu_busy states.
|
2022-07-22 23:20:37 -05:00 |
|
Katherine Parry
|
655e2d3810
|
merged radix-2 sqrt into divider - doesnt work yet
|
2022-07-23 00:41:18 +00:00 |
|
slmnemo
|
bfced6bfe8
|
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
|
2022-07-22 17:13:38 -07:00 |
|
slmnemo
|
ca4511b6dc
|
Fixed UART FIFO bugs and added FIFO tests
|
2022-07-22 17:13:19 -07:00 |
|
Katherine Parry
|
b3d932cd61
|
divider sizes reworked to match book
|
2022-07-22 22:02:04 +00:00 |
|
David Harris
|
d22587090b
|
Reset MSR on read
|
2022-07-22 04:29:27 +00:00 |
|
slmnemo
|
3d2c6683d8
|
Fixed UART bug related to parity and MSR/LSR
|
2022-07-21 20:35:46 -07:00 |
|
Katherine Parry
|
fbe8bb2298
|
radix-4 division integrated into srt - not tested
|
2022-07-21 19:38:06 +00:00 |
|
Katherine Parry
|
7950a675ea
|
added input enables and improved forwarding
|
2022-07-21 01:20:06 +00:00 |
|
Katherine Parry
|
a30d9c6bd8
|
turn off 2 word store durring non-fp instructions
|
2022-07-20 21:57:23 +00:00 |
|
Ross Thompson
|
1cad05fef9
|
Minor cleanup of cache.
|
2022-07-19 23:04:23 -05:00 |
|
Ross Thompson
|
8698799077
|
Reverted to fetched the demand cache line first then doing the eviction. This is important because of an optimization in the replacement policy. The replacement policy updates the LRU 1 cycle late and reads the LRU 1 cycle late for critical path timing. This means doing the eviction first requires an initial 1 cycle delay but this delay has to be applied to all misses because we don't know if an eviction is required. Since reading the demand line first is logically ok so long as it is not written to the sram until after the eviction.
|
2022-07-19 22:42:25 -05:00 |
|
Katherine Parry
|
b26297e874
|
moved ctrl signal registers into fctrl, also a lot of code cleaning
|
2022-07-20 02:27:39 +00:00 |
|
cturek
|
0f94177765
|
small changes
|
2022-07-20 01:36:25 +00:00 |
|
Katherine Parry
|
d61f84e751
|
oprimized zeros and replaced complex ?: with always_comb
|
2022-07-19 23:44:37 +00:00 |
|
Ross Thompson
|
a79e5e11f6
|
Merged together the cache speed updates with the cache sram changes. The fstore2 changes still need to be added.
|
2022-07-18 23:37:18 -05:00 |
|
Katherine Parry
|
514674417e
|
moved Se into execute stage
|
2022-07-19 01:10:10 +00:00 |
|
Katherine Parry
|
64b3e4117b
|
reworked fmashiftcalc to match book
|
2022-07-19 00:04:24 +00:00 |
|
David Harris
|
9fd772ce83
|
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally
|
2022-07-18 23:11:12 +00:00 |
|
Katherine Parry
|
cce5fb8dfd
|
moved Ss to execute stage
|
2022-07-18 20:48:56 +00:00 |
|
Katherine Parry
|
7268b4b334
|
removed underflow from inexactct calculation
|
2022-07-18 17:51:18 +00:00 |
|
Katherine Parry
|
d6f1fc12db
|
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally
|
2022-07-18 17:31:29 +00:00 |
|
Katherine Parry
|
0210718f19
|
renamed signals in ocde to match book
|
2022-07-18 17:31:17 +00:00 |
|
Ross Thompson
|
0ef6137ab9
|
Added degree of freedom to cache/sram. The sram width in bits is no longer defined by XLEN, but instead a separate parameter. This is decoupled from LINELEN, XLEN, and WORDLEN.
|
2022-07-17 21:05:31 -05:00 |
|
Ross Thompson
|
8356e5d742
|
Updated cache sram's to use 1 sram for all words in a way. Still needs to modified to support subdivision by max physical sram width.
|
2022-07-17 16:20:04 -05:00 |
|
David Harris
|
03f573351a
|
Rewrote convert shift calculation with always for ease of reading
|
2022-07-17 16:40:58 +00:00 |
|
David Harris
|
622773343f
|
restored intPending logic to be sticky for PLIC
|
2022-07-16 17:43:31 -07:00 |
|
Katherine Parry
|
e3ed40620c
|
forgot some files
|
2022-07-15 21:42:45 +00:00 |
|
Katherine Parry
|
5cb9c9f319
|
merged floating-point radix-2 divider with radix-4
|
2022-07-15 20:16:59 +00:00 |
|
Katherine Parry
|
2fe8b6e34c
|
fixed error in divsqrt
|
2022-07-14 18:16:00 +00:00 |
|
Katherine Parry
|
66bef379cb
|
renamed a file to fit diagram
|
2022-07-13 23:44:54 +00:00 |
|
Katherine Parry
|
3dcddf8453
|
some code cleanup
|
2022-07-13 15:28:22 -07:00 |
|
Katherine Parry
|
b874c5c05d
|
removed minus 1 case in rounding
|
2022-07-13 15:01:38 -07:00 |
|
Katherine Parry
|
b45b3baec2
|
removed the +1 in the cvt
|
2022-07-13 09:41:35 -07:00 |
|
Katherine Parry
|
3c1bea1104
|
removed warnings and took a mux out of the critical path
|
2022-07-12 18:32:17 -07:00 |
|
Katherine Parry
|
12a54161c0
|
found the bug in the store modification
|
2022-07-12 22:42:19 +00:00 |
|
Katherine Parry
|
18d7fee541
|
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally
|
2022-07-12 22:37:20 +00:00 |
|
Katherine Parry
|
1267d33d3c
|
forgot a file
|
2022-07-11 18:31:51 -07:00 |
|
Katherine Parry
|
ba339fc794
|
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
|
2022-07-11 18:30:29 -07:00 |
|
Katherine Parry
|
bea4ec078d
|
variable interations implemented in radix-4 divider
|
2022-07-11 18:30:21 -07:00 |
|
David Harris
|
03a20610aa
|
added comment about checking SRAM size
|
2022-07-10 12:48:51 +00:00 |
|
David Harris
|
d1a7832dd9
|
added comment about RAMs in cacheway
|
2022-07-10 12:47:34 +00:00 |
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Katherine Parry
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62205ebb3b
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renamed FLoad2 to FStore2
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2022-07-09 00:26:45 +00:00 |
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Katherine Parry
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97e7e619d9
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moved fpu ieu write data mux to lsu
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2022-07-08 23:56:57 +00:00 |
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Katherine Parry
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c56fdd7e0f
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2022-07-08 12:30:50 -07:00 |
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Katherine Parry
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88b4f9b40a
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renamed signals in cvt and prostproc
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2022-07-08 12:30:43 -07:00 |
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James Stine
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99fed5d59f
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Update SRAM to /proj/wally
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2022-07-08 08:09:55 -05:00 |
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David Harris
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87ea95e6c5
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erge branch 'main' of https://github.com/davidharrishmc/riscv-wally
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2022-07-08 09:09:07 +00:00 |
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David Harris
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5ae88dbef0
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Moved HWSTRB to ahblite, factored out of peripherals. Moved old AHB peripherals to unusedsrc
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2022-07-08 09:09:02 +00:00 |
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David Harris
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96cc66d151
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Adjusting byte writes to RAM
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2022-07-08 08:45:21 +00:00 |
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David Harris
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38ef8eebbb
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Removed subwordwrite mention in cache because sww is needed to replicate data across byte enables
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2022-07-08 08:44:37 +00:00 |
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David Harris
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234175f236
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Removed unused swbytemask from CLINT
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2022-07-08 08:43:24 +00:00 |
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Katherine Parry
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b67792086c
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moved unsused division code again
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2022-07-07 16:41:26 -07:00 |
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Katherine Parry
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b1e2a1e5a1
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Revert "moved old divsqrt to unusedsrc"
This reverts commit 5dd07c76bd.
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2022-07-07 16:29:17 -07:00 |
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Katherine Parry
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5dd07c76bd
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moved old divsqrt to unusedsrc
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2022-07-07 16:09:56 -07:00 |
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Katherine Parry
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75a8cea4e4
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srt divider merged into fpu
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2022-07-07 16:01:33 -07:00 |
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David Harris
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425fec0f41
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally
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2022-07-07 22:00:59 +00:00 |
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Katherine Parry
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c581fba4aa
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modified wally shared
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2022-07-07 21:59:43 +00:00 |
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David Harris
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f865994ba1
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fixing port errors
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2022-07-07 21:57:10 +00:00 |
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Katherine Parry
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7771f7b3eb
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added load and store test
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2022-07-07 21:48:51 +00:00 |
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David Harris
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f2915129ab
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Preliminary SRAM integration
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2022-07-07 19:56:20 +00:00 |
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David Harris
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21fb120aac
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally
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2022-07-06 23:43:05 +00:00 |
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Ross Thompson
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d716c25275
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Fixed an issue with direct map cache's nextway logic.
Also found a small error in the replacement policy.
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2022-07-06 18:34:30 -05:00 |
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Madeleine Masser-Frye
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ad29e19a27
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fixed width mismatch for rv64 ieuadrM and readdatawordM
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2022-07-06 22:39:35 +00:00 |
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David Harris
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529f48ed58
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally
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2022-07-06 13:26:26 +00:00 |
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David Harris
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76302a8599
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PLIC and UART passing tests on APB
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2022-07-06 13:26:14 +00:00 |
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Madeleine Masser-Frye
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52562c9190
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new priority onehot module for better area/time
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2022-07-06 00:08:59 +00:00 |
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Madeleine Masser-Frye
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b5454f3a55
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took first match out of pmpadrdec
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2022-07-06 00:02:01 +00:00 |
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Madeleine Masser-Frye
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d8ea12c6f4
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fixed concatenation syntax
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2022-07-05 22:36:54 +00:00 |
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David Harris
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72e216d053
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APB CLINT passing regression
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2022-07-05 15:51:35 +00:00 |
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David Harris
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5f5ad77d4a
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Modified uncore to use AHB bridge to GPIO
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2022-07-05 05:02:21 +00:00 |
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David Harris
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c8ac05ba7b
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AHB bridge for gpio
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2022-07-05 05:01:59 +00:00 |
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David Harris
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ca95b46de5
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Added reference to Schmookler01 for LOA
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2022-07-05 05:01:12 +00:00 |
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David Harris
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1a356312b2
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Added comments to PLIC about likely bug
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2022-07-05 05:00:29 +00:00 |
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David Harris
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abfd935e06
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removed delay in ahblite
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2022-07-05 04:59:28 +00:00 |
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Katherine Parry
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2fc795ca70
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added missing files
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2022-07-03 21:40:47 -07:00 |
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Katherine Parry
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8ac722f693
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Renaming signals to match chapter
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2022-07-03 12:26:22 -07:00 |
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David Harris
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0fa35acbc5
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally
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2022-07-02 19:37:14 +00:00 |
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David Harris
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89b319aa1b
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FMA ZAligned name
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2022-07-02 19:35:13 +00:00 |
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Katherine Parry
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8930cdcfbb
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some prostprocessing cleanup
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2022-07-01 14:55:46 -07:00 |
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Katherine Parry
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8f98f3bfab
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added rv32 double precision stores - untested
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2022-06-28 21:33:31 +00:00 |
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Katherine Parry
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0417a6a45b
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very basic early termination passes testfloat 64-bit tests
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2022-06-28 00:16:22 +00:00 |
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Katherine Parry
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a5fb60eb1a
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radix-4 early termination working for special cases - not working completely
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2022-06-27 20:43:55 +00:00 |
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Katherine Parry
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adaee899bb
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radix-4 divider passing all double precision testfloat tests
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2022-06-27 17:04:51 +00:00 |
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Katherine Parry
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70a1bb8377
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fixed commented out error and removed killprod from result selection
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2022-06-25 01:42:23 +00:00 |
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Katherine Parry
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fa1623551c
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passing regression again
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2022-06-25 00:31:32 +00:00 |
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Katherine Parry
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6d6cc7bb48
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commented out error - also some divider bugs fixed
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2022-06-25 00:04:53 +00:00 |
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Katherine Parry
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43882d5878
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modified result select to account for x/inf
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2022-06-24 21:23:15 +00:00 |
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Katherine Parry
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a85a868b56
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radix 4 division denormal result handeling
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2022-06-24 21:02:50 +00:00 |
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Katherine Parry
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9eefba5b58
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added denormal input handeling - radix 4
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2022-06-24 19:41:40 +00:00 |
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Katherine Parry
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ff1fae74d8
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division by zero added
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2022-06-24 01:09:44 +00:00 |
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Katherine Parry
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ec2c446c7e
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forgot a file
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2022-06-23 23:01:30 +00:00 |
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Katherine Parry
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b16e55906a
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div debug - accounted for 1 bit normalization in exponent calculation
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2022-06-23 22:59:43 +00:00 |
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Katherine Parry
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749d405da8
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lint warning fix
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2022-06-23 22:37:44 +00:00 |
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Katherine Parry
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de71773d69
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added radix-4 0/d handling
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2022-06-23 22:36:19 +00:00 |
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slmnemo
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bca8fe1694
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Removed big64.txt reference, fixing a warning
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2022-06-23 14:39:53 -07:00 |
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David Harris
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44216b3967
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Fixed typo in clint
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2022-06-23 21:27:46 +00:00 |
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David Harris
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d969edeb99
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Reset mtimecmp in clint
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2022-06-23 21:20:55 +00:00 |
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Katherine Parry
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d7a363aaa7
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fixt lint error
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2022-06-23 16:11:50 +00:00 |
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Katherine Parry
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1612daa294
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Testfloat running division - not passing
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2022-06-23 00:07:34 +00:00 |
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Madeleine Masser-Frye
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6229779b97
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally
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2022-06-21 20:31:06 +00:00 |
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Madeleine Masser-Frye
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3c08861479
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switched comparator to dc flip version
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2022-06-21 20:30:33 +00:00 |
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Katherine Parry
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03d823f5d7
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added fld in rv32 - needs testing
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2022-06-20 22:53:13 +00:00 |
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