David Harris 8444eca57c Simplified FPU-LSU interface to skip IEU		2022-08-22 13:29:20 -07:00
..
cache	Updated fpga test bench.	2022-08-21 15:59:54 -05:00
ebu	Fixed fstore2 in cache?	2022-08-01 22:04:44 -05:00
fpu	Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main	2022-08-22 13:28:54 -07:00
generic	moved CSA to generic	2022-08-22 08:41:23 +00:00
hazard	Simplified FPU-LSU interface to skip IEU	2022-08-22 13:28:51 -07:00
ieu	Simplified FPU-LSU interface to skip IEU	2022-08-22 13:28:51 -07:00
ifu	Updated fpga test bench.	2022-08-21 15:59:54 -05:00
lsu	Simplified FPU-LSU interface to skip IEU	2022-08-22 13:29:20 -07:00
mmu	took first match out of pmpadrdec	2022-07-06 00:02:01 +00:00
muldiv	Clean up unused signals	2022-05-12 14:49:58 +00:00
ppa	cleanup, plots for paper	2022-06-15 18:28:36 +00:00
privileged	Provided sfencevmaM to hazard unit and renamed TLBFlush signals to sfencevma going into LSU/IFU. Preparing for SFENCE.VMA to flush the pipeline, but that is not yet working.	2022-06-02 14:18:55 +00:00
uncore	Added parity and stop bit tests to UART	2022-07-28 04:35:51 +00:00
wally	Removed logic from Verilog wrapper.	2022-08-21 14:07:43 -05:00
sdc	piplined directory cleanup	2022-01-07 12:43:50 +00:00