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removed simpleram and modified dtim to use bram1p1rw
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@ -1,48 +0,0 @@
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///////////////////////////////////////////
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// simpleram.sv
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//
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// Written: David_Harris@hmc.edu 9 January 2021
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// Modified:
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//
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// Purpose: On-chip SIMPLERAM, external to core
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//
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// A component of the Wally configurable RISC-V project.
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//
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// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
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//
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// MIT LICENSE
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// Permission is hereby granted, free of charge, to any person obtaining a copy of this
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// software and associated documentation files (the "Software"), to deal in the Software
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// without restriction, including without limitation the rights to use, copy, modify, merge,
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// publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons
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// to whom the Software is furnished to do so, subject to the following conditions:
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//
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// The above copyright notice and this permission notice shall be included in all copies or
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// substantial portions of the Software.
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//
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// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED,
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// INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR
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// PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
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// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE
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// OR OTHER DEALINGS IN THE SOFTWARE.
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////////////////////////////////////////////////////////////////////////////////////////////////
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`include "wally-config.vh"
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module simpleram #(parameter BASE=0, RANGE = 65535) (
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input logic clk,
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input logic [31:0] a,
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input logic we,
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input logic [`LLEN/8-1:0] ByteMask,
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input logic [`LLEN-1:0] wd,
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output logic [`LLEN-1:0] rd
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);
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localparam ADDR_WDITH = $clog2(RANGE/8);
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localparam OFFSET = $clog2(`LLEN/8);
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bram1p1rw #(`LLEN/8, 8, ADDR_WDITH)
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memory(.clk, .we, .bwe(ByteMask), .addr(a[ADDR_WDITH+OFFSET-1:OFFSET]), .dout(rd), .din(wd));
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endmodule
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@ -5,8 +5,8 @@
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// March 29, 2022
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// Modified: Based on UG901 vivado documentation.
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//
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// Purpose: On-chip SIMPLERAM, external to core
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//
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/// Purpose: On-chip RAM array
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//
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// A component of the Wally configurable RISC-V project.
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//
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// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
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@ -5,7 +5,7 @@
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// March 29, 2022
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// Modified: Based on UG901 vivado documentation.
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//
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// Purpose: On-chip SIMPLERAM, external to core
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// Purpose: On-chip RAM array
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//
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// A component of the Wally configurable RISC-V project.
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//
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@ -47,13 +47,19 @@ module dtim(
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output logic DCacheStallM,
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output logic DCacheCommittedM,
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output logic DCacheMiss,
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output logic DCacheAccess);
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simpleram #(.BASE(`UNCORE_RAM_BASE), .RANGE(`UNCORE_RAM_RANGE)) ram (
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.clk, .ByteMask(ByteMaskM),
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.a(CPUBusy | LSURWM[0] | reset ? IEUAdrM[31:0] : IEUAdrE[31:0]), // move mux out; this shouldn't be needed when stails are handled differently ***
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.we(LSURWM[0] & Cacheable & ~TrapM), // have to ignore write if Trap.
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.wd(WriteDataM), .rd(ReadDataWordM));
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output logic DCacheAccess
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);
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logic we;
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// localparam ADDR_WDITH = $clog2(`TIM_RAM_RANGE/8); // *** replace with tihs when defined
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localparam ADDR_WDITH = $clog2(`UNCORE_RAM_RANGE/8); // *** this is the wrong size
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localparam OFFSET = $clog2(`LLEN/8);
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assign we = LSURWM[0] & Cacheable & ~TrapM; // have to ignore write if Trap.
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bram1p1rw #(`LLEN/8, 8, ADDR_WDITH)
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ram(.clk, .we, .bwe(ByteMaskM), .addr(IEUAdrE[ADDR_WDITH+OFFSET-1:OFFSET]), .dout(ReadDataWordM), .din(WriteDataM));
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// since we have a local memory the bus connections are all disabled.
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// There are no peripherals supported.
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@ -200,8 +200,6 @@ module lsu (
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// use the same UNCORE_RAM_BASE addresss for both the DTIM and any RAM in the Uncore.
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if (`DMEM) begin : dtim
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// *** directly instantiate RAM or ROM here. Instantiate SRAM1P1RW.
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// Merge SimpleRAM and SRAM1p1rw into one that is good for synthesis and RAM libraries and flops
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dtim dtim(.clk, .reset, .CPUBusy, .LSURWM, .IEUAdrM, .IEUAdrE, .TrapM, .WriteDataM(LSUWriteDataM), //*** fix the dtim FinalWriteData
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.ReadDataWordM(ReadDataWordM[`XLEN-1:0]), .BusStall, .LSUBusWrite,.LSUBusRead, .BusCommittedM,
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.DCacheStallM, .DCacheCommittedM, .ByteMaskM(ByteMaskM[`XLEN/8-1:0]), .Cacheable(CacheableM),
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@ -246,6 +246,7 @@ module testbench;
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logic HSELEXT;
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logic [31:0] HADDR;
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logic [`AHBW-1:0] HWDATA;
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logic [`XLEN/8-1:0] HWSTRB;
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logic HWRITE;
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logic [2:0] HSIZE;
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logic [2:0] HBURST;
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@ -270,7 +271,7 @@ module testbench;
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// Wally
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wallypipelinedsoc dut(.clk, .reset, .reset_ext,
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.HRDATAEXT, .HREADYEXT, .HREADY, .HSELEXT, .HRESPEXT, .HCLK,
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.HRESETn, .HADDR, .HWDATA, .HWRITE, .HSIZE, .HBURST, .HPROT,
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.HRESETn, .HADDR, .HWDATA, .HWRITE, .HWSTRB, .HSIZE, .HBURST, .HPROT,
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.HTRANS, .HMASTLOCK,
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.TIMECLK('0), .GPIOPinsIn, .GPIOPinsOut, .GPIOPinsEn,
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.UARTSin, .UARTSout,
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