David Harris e70b28f7f6 FMA cleanup		2022-08-02 07:42:32 -07:00
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cache	Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main	2022-08-01 22:09:11 -05:00
ebu	Fixed fstore2 in cache?	2022-08-01 22:04:44 -05:00
fpu	FMA cleanup	2022-08-02 07:42:32 -07:00
generic	removed warnings and took a mux out of the critical path	2022-07-12 18:32:17 -07:00
hazard	srt divider merged into fpu	2022-07-07 16:01:33 -07:00
ieu	added rv32 double precision stores - untested	2022-06-28 21:33:31 +00:00
ifu	Fixed fstore2 in cache?	2022-08-01 22:04:44 -05:00
lsu	Fixed fstore2 in cache?	2022-08-01 22:04:44 -05:00
mmu	took first match out of pmpadrdec	2022-07-06 00:02:01 +00:00
muldiv	Clean up unused signals	2022-05-12 14:49:58 +00:00
ppa	cleanup, plots for paper	2022-06-15 18:28:36 +00:00
privileged	Provided sfencevmaM to hazard unit and renamed TLBFlush signals to sfencevma going into LSU/IFU. Preparing for SFENCE.VMA to flush the pipeline, but that is not yet working.	2022-06-02 14:18:55 +00:00
uncore	Added parity and stop bit tests to UART	2022-07-28 04:35:51 +00:00
wally	pulled swbbytemask out of subword write.	2022-08-01 20:48:45 -05:00
sdc	piplined directory cleanup	2022-01-07 12:43:50 +00:00