cvw/pipelined/src
2022-07-24 15:40:52 -05:00
..
cache Don't use this commit yet. Untested. 2022-07-24 15:40:52 -05:00
ebu Moved HWSTRB to ahblite, factored out of peripherals. Moved old AHB peripherals to unusedsrc 2022-07-08 09:09:02 +00:00
fpu merged radix-2 sqrt into divider - doesnt work yet 2022-07-23 00:41:18 +00:00
generic removed warnings and took a mux out of the critical path 2022-07-12 18:32:17 -07:00
hazard srt divider merged into fpu 2022-07-07 16:01:33 -07:00
ieu added rv32 double precision stores - untested 2022-06-28 21:33:31 +00:00
ifu signal name cleanup. 2022-07-22 23:36:27 -05:00
lsu Don't use this commit yet. Untested. 2022-07-24 15:40:52 -05:00
mmu took first match out of pmpadrdec 2022-07-06 00:02:01 +00:00
muldiv Clean up unused signals 2022-05-12 14:49:58 +00:00
ppa cleanup, plots for paper 2022-06-15 18:28:36 +00:00
privileged Provided sfencevmaM to hazard unit and renamed TLBFlush signals to sfencevma going into LSU/IFU. Preparing for SFENCE.VMA to flush the pipeline, but that is not yet working. 2022-06-02 14:18:55 +00:00
uncore Fixed UART FIFO bugs and added FIFO tests 2022-07-22 17:13:19 -07:00
wally Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally 2022-07-12 22:37:20 +00:00
sdc piplined directory cleanup 2022-01-07 12:43:50 +00:00