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1286 Commits

Author SHA1 Message Date
David Harris
691c1c0dd0 ALUControl cleanup 2021-12-19 13:53:45 -08:00
Katherine Parry
ece9e9df84 fixed some small errors in FMA 2021-12-19 13:51:46 -08:00
Ross Thompson
202203904c Corrected the LSU's fsm for stalling CPU. Removed state from hptw fsm. 2021-12-19 15:10:33 -06:00
Ross Thompson
9adcf86a40 Modified the icache memory to read using the virtual (non physical) address in the PCNextF stage. 
This allows recovering from an ITLBMiss to be 1 cycle after and simplifies the hptw slightly.
 2021-12-19 14:57:42 -06:00
Ross Thompson
0257c08641 Renamed MemAdrM to IEUAdrM. This will free the name MemAdrm for use in the DCache. 2021-12-19 14:00:30 -06:00
Ross Thompson
620f4a58d4 Adds FSM to LSU which will handle the interactions between the hptw and dcache. This will dramatically simplify the dcache by removing all walker states. 2021-12-19 13:55:57 -06:00
Ross Thompson
fdf493bd47 minro change. comments about needed changes in dcache. 2021-12-19 13:53:02 -06:00
David Harris
c04c56dae1 Renamed zero to eq in flag generation 2021-12-19 11:49:15 -08:00
David Harris
e5d2d7a3fd Controller fix 2021-12-18 22:08:23 -08:00
David Harris
8a597390e0 Renamed RD1D to R1D, etc. 2021-12-18 21:26:00 -08:00
David Harris
7fb4213751 Simplified shifter right input 2021-12-18 10:25:40 -08:00
Ross Thompson
f601b3ae53 Merge branch 'tlb_fixes' into main 2021-12-18 12:24:17 -06:00
David Harris
d97d34ee32 Simplified Shifter Right input 2021-12-18 10:21:17 -08:00
David Harris
852c521328 Shared ALU mux input for shifts 2021-12-18 10:08:52 -08:00
David Harris
a7d7f852a6 Factored out common parts of shifter 2021-12-18 10:01:12 -08:00
David Harris
7868c0da55 Cleaning shifter 2021-12-18 09:43:09 -08:00
David Harris
b453454b24 Moved W64 truncation after result mux 2021-12-18 09:27:25 -08:00
David Harris
2a5a7eff82 Forwarding logic factoring 2021-12-18 05:40:38 -08:00
David Harris
1212e21eba Simplified FWriteInt interfaces by merging into RegWrite 2021-12-18 05:36:32 -08:00
Ross Thompson
2f86e84843 Merge remote-tracking branch 'origin/tlb_fixes' into main 2021-12-17 14:40:29 -06:00
Ross Thompson
79ec4161b6 Added more debugging code for FPGA. 2021-12-17 14:40:25 -06:00
Ross Thompson
5264577dcf Possible fix for icache deadlock interaction with hptw. 2021-12-17 14:38:25 -06:00
David Harris
3a9071e509 Renamed MemAdrE to IEUAdrE and moved the MemAdrM flop from IEU to LSU to reduce wires crossing hierarchies 2021-12-15 12:10:45 -08:00
David Harris
f0059b7b3a IEU cleanup: 2021-12-15 11:38:26 -08:00
Ross Thompson
9f798250ea Oups missed files in the last commit. 2021-12-15 10:25:08 -06:00
David Harris
f4957fdac1 Renamed dtim->ram and boottim ->bootrom 2021-12-14 13:43:06 -08:00
Ross Thompson
45b38ea9fe Comments for dcache and icache refactoring. 2021-12-14 14:46:29 -06:00
David Harris
eb33021f40 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-12-14 11:15:58 -08:00
David Harris
dd0d4c0add ALU and datapath cleanup 2021-12-14 11:15:47 -08:00
Ross Thompson
f061a26411 Cleaned up fpga synthesis script. 2021-12-13 18:26:54 -06:00
Ross Thompson
b9c8b808ea Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-12-13 17:16:20 -06:00
Ross Thompson
7d00649b61 Formating changes to cache fsms. 2021-12-13 17:16:13 -06:00
Ross Thompson
5361f69639 Fixed some typos in the dcache ptw interaction documentation. 2021-12-13 15:47:20 -06:00
David Harris
74cf0eb96a Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-12-13 07:57:49 -08:00
David Harris
1ca949c0bb Simplified ALU and source multiplexers pass tests 2021-12-13 07:57:38 -08:00
kwan
5ede8126fd priviledge .* removed, passed regression 2021-12-13 00:34:43 -08:00
kwan
b05bc3c19e test 2021-12-13 00:31:51 -08:00
kwan
83dae9d774 priviledge .* fixed, passed local regression 2021-12-13 00:22:01 -08:00
Ross Thompson
8e39034dbd Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-12-12 17:33:29 -06:00
Ross Thompson
2f282e5570 Revert "Privilige .*s removed" 
This reverts commit 471f267987.
 2021-12-12 17:31:57 -06:00
Ross Thompson
fdbb7b6ef3 Revert "Priviledged .* removed" 
This reverts commit 96ac298596.
 2021-12-12 17:31:39 -06:00
Ross Thompson
547093b705 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-12-12 17:21:51 -06:00
Ross Thompson
bb79f70a63 Modified FPGA to add additional signals to ILA. Created advanced trigger for ILA using vivado's tsm language. 2021-12-12 17:21:44 -06:00
Ross Thompson
b88ec949cf Added proper credit to Richard Davis, the author of the original sd card reader. 2021-12-12 15:05:50 -06:00
kwan
96ac298596 Priviledged .* removed 2021-12-12 09:55:45 -08:00
kwan
471f267987 Privilige .*s removed 2021-12-12 09:54:14 -08:00
David Harris
d3c3ab3e85 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-12-12 05:49:31 -08:00
Ross Thompson
cd59809e42 Fixed numerous errors in the preformance counter updates. 
Fixed dcache reporting of access and misses.
Added performance counter tracking to coremark.
 2021-12-09 11:44:12 -06:00
slmnemo
3ff994f50d Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 
help
 2021-12-08 14:09:58 -08:00
slmnemo
094f45e28b Removed .* from /wally-pipelined/src/uncore/uart.sv 2021-12-08 14:02:53 -08:00
Ross Thompson
a55018b67a Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-12-08 15:50:43 -06:00
Ross Thompson
3bdda9687a Fixed some issues with the SDC having a different counter. When this is copied into synthesis the file names where the same and it gave a conflict. 
Remove preload from dtim.
 2021-12-08 15:50:15 -06:00
David Harris
9e2c3bef3c Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-12-08 13:48:49 -08:00
David Harris
0b63c1cede Refactored IEU/ALU logic 2021-12-08 13:48:04 -08:00
Noah Limpert
e97dd080a0 updated fcmp.sv instantiation to remove x*'s 2021-12-08 13:34:33 -08:00
David Harris
a174c8b4d7 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-12-08 12:33:59 -08:00
David Harris
5d4014d351 Refactoring ALU and datapath muxes 2021-12-08 12:33:53 -08:00
slmnemo
d58f318d39 Removed .*s from wally-pipelined/src/uncore/uncore.sv 2021-12-08 01:03:02 -08:00
slmnemo
52b4802600 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-12-08 00:26:13 -08:00
Noah Limpert
feb21d1c4a removed .* instantiation from ieu.sv and datapth.sv in ieu folder 2021-12-08 00:24:27 -08:00
slmnemo
acacd13ffc Removed .* from mmu instance inside lsu.sv. 2021-12-08 00:15:30 -08:00
Katherine Parry
d0e708f239 FMA uses one LOA 2021-12-07 14:15:43 -08:00
bbracker
d459e35645 undo intentionally breaking commit 2021-12-07 13:43:47 -08:00
bbracker
3379b74bb2 intentionally breaking commit 2021-12-07 13:27:34 -08:00
bbracker
cf61187273 undo intentionally breaking commit 2021-12-07 13:27:06 -08:00
bbracker
69f025a642 intentionally breaking commit 2021-12-07 13:23:19 -08:00
Ross Thompson
8bb3d51aad Added generate around the dtim preload. 
Added readme to explain FPGA.
 2021-12-07 13:12:47 -06:00
Ross Thompson
3d829dbbd3 Fixed two issues. 
First the xci files already include the xdc constraints for each IP block. There is no need to include the xdc files explicitly.
Second the bidir buffer for the sd card was connected backwards.
 2021-12-07 12:15:50 -06:00
Ross Thompson
517cae796c Fixed more constraint issues in fpga. 
Added back in the ILA.
Design does not work yet.  Stil having issues with order of automatic
clock and I/O constraint ordering.
Added back in the preload for the boottim.
 2021-12-05 15:14:18 -06:00
Ross Thompson
74ffb48c0a Mostly integrated FPGA flow into main branch. Not all tests passing yet. 2021-12-02 18:00:32 -06:00
Ross Thompson
b7e8c74e61 Merge branch 'fpga' into main 2021-12-02 14:28:10 -06:00
kwan
e4f214090d .* resolved in ifu.sv 2021-12-02 10:32:35 -08:00
kwan
2a77bc8053 .* in ifu/ifu.sv eliminated 2021-12-02 09:45:55 -08:00
Ross Thompson
d7df9c1054 Fixed uart for FPGA config after merge. This still needs some work. 2021-11-29 16:07:54 -06:00
Ross Thompson
8e4eacc18e Merge branch 'main' into fpga 2021-11-29 10:10:37 -06:00
Ross Thompson
e43aa6ead4 Merge branch 'main' into fpga 2021-11-29 10:06:53 -06:00
Noah Limpert
cb77c1db3a updated fpu instantion on wallypiplinedhart to remove .*, updated spacing as well 2021-11-24 23:22:04 -08:00
Noah Limpert
e66fdd3f80 replaced .* instation of priv module on wallypiplinedhart 2021-11-24 22:58:59 -08:00
Noah Limpert
0cd31bfc1f Made abhlite instation on wallypipehart more clear, updated spacing for consistency 2021-11-24 22:48:01 -08:00
Noah Limpert
8a64510ee4 updated module instation of LSU on wallypiplinedhard 2021-11-24 22:09:39 -08:00
Ross Thompson
b909375289 Missed another change to uart. 2021-11-23 10:20:47 -06:00
Ross Thompson
fe00729d7c Fixed syntax error which modelsim did not detect in my changes for making uart work with qemu's simulation. 2021-11-23 10:00:32 -06:00
Ross Thompson
e309017ec4 Added QEMU hack for initial LCR value in uart. 2021-11-22 15:23:19 -06:00
Ross Thompson
e568068c78 Hack added to uart so QEMU simulation can work with an ultra fast baud rate relative to the clock speed. 2021-11-22 15:20:54 -06:00
Ross Thompson
fcd14828d4 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-11-22 11:30:14 -06:00
bbracker
d90d708cf9 activate STVAL for buildroot 2021-11-21 10:40:28 -08:00
Ross Thompson
c661bb4894 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-11-20 22:44:45 -06:00
Ross Thompson
baa98e7015 Reversed bit order in uart. 2021-11-20 22:43:05 -06:00
Ross Thompson
2f85ac7f38 Fixed a very complex interaction between interrupts, the icache, dcache, and hptw. 
If an interrupt occurred at the start of an ITLB miss or DTLB miss the page table
walk should be aborted before starting.
 2021-11-20 22:35:47 -06:00
slmnemo
870549c01a Removed .* from hazard hzu(.*). 2021-11-17 14:21:23 -08:00
slmnemo
a98dcd11ee Removed .* from hazard hzu(.*) in wallypipelinedhart.sv. 2021-11-17 14:08:08 -08:00
slmnemo
fed613dc72 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-11-17 13:38:51 -08:00
slmnemo
f4380faa4e removed .* from muldiv.sv (REAL) 2021-11-17 13:37:50 -08:00
Noah Limpert
0ccc7d5fe8 ieu variable naming changed for clarity 2021-11-17 13:24:28 -08:00
slmnemo
9fb26d5a61 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-11-17 13:23:20 -08:00
slmnemo
573f8b0c42 Removed .*s from muldiv.sv 2021-11-17 13:23:12 -08:00
Noah Limpert
832b23b8a4 Updated IFU variable naming for clarity 2021-11-17 12:39:05 -08:00
Kip Macsai-Goren
3f76549a7d renamed presrc to forwardedSrc, replaced SrcAE and SrcBE with Forwarded src in the muldiv 2021-11-17 10:53:17 -08:00
Ross Thompson
3b8bdc7b2d Created separate memory interface for the ddr4 fpga memory from the soc internal memory dtim. 2021-11-17 12:47:19 -06:00
Ross Thompson
11a21899d5 Fixed uart by reversing the bit order on transmit. 
Set prescale to 0.
 2021-11-17 10:32:41 -06:00
Ross Thompson
4af7a27d87 Have linux booting. Not sure about uart, but uart is now part of the ILA and I can see TX changing. 2021-11-12 17:37:07 -06:00
Ross Thompson
b8572d6a2a Changed several things. 
Removed the need to use async flip flops in SDC.
Added arrs, a synchronizer for reset.
I think this works with the real FPGA hardware.
The last build did not include this arrs but it worked.
 2021-11-12 11:13:50 -06:00
Kevin
b34569c358 changed code aligner to run recursively on a root directory 
-only runs the aligner on .sv files
-runs recursively on sub-directories
 2021-11-03 10:49:34 -07:00
David Harris
4b57af9cff PIPELINE test running 2021-11-01 12:44:35 -07:00
Ross Thompson
8aad95366d Fixed the 4 way set associative pseudo LRU replacement policy. 2021-10-29 12:46:02 -05:00
Ross Thompson
f61fcd25a9 Possible fix for the incorrect behavior of the pseudo LRU replacement policy for 4 ways set associative caches. 2021-10-29 11:03:37 -05:00
Ross Thompson
54c714d222 Applied batch from fpga branch which fixes the dcache fence bug. The should cause the dcache to flush all dirty cache lines to main memory. The bug caused the dirty reset to clear each way for a particular line. 2021-10-28 11:07:18 -05:00
Noah Limpert
21ea270fe2 Have replaced .* with signal names in ifu 2021-10-27 13:45:37 -07:00
koooo142857
0a33b0904d aligned all files in ifu folder 2021-10-27 12:43:55 -07:00
David Harris
9cfb8deaab Fixed FResultSelM to select proper flags 2021-10-27 11:02:42 -07:00
Ross Thompson
d98baf90a3 Replaced async reset flip flops with sync reset flip flops in cache and bpread. 2021-10-27 09:57:11 -05:00
Ross Thompson
0817ef20f1 Linux now boots fpga. 2021-10-26 16:49:16 -05:00
David Harris
1a6fb2fad9 Forgot to save cacheway merge 2021-10-26 08:38:13 -07:00
David Harris
79c1395967 merging changes 2021-10-26 08:34:36 -07:00
David Harris
44de52a05a Synchronous reset in non-flop blocks 2021-10-26 08:30:35 -07:00
Ross Thompson
09b3549efd Fixed another critical path in the caches. 2021-10-25 22:05:11 -05:00
Ross Thompson
cb7015a690 Fixed the timing issue in the cache replacement polcy. 2021-10-25 18:00:23 -05:00
Ross Thompson
6c92d3267f Fixed bug with the changes to sram1rw. 2021-10-25 16:11:41 -05:00
Ross Thompson
c963ea1a64 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-10-25 15:36:21 -05:00
Ross Thompson
694b3fbb6f Possible fix for critical path timing in caches. 2021-10-25 15:33:33 -05:00
Ross Thompson
2f4ee26b60 Fixed issue with dtim (fpga) external abhlite select not triggering. 
Setup the bootloader (bios.s) to copy 127MB and blink LEDs for 5 seconds with 1 second period.
 2021-10-25 14:51:54 -05:00
bbracker
2c9c9328a9 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-10-25 12:25:37 -07:00
Ross Thompson
f7583d0e0d Updated uncore to use sdc. 
Fixed bug with fence instruction not correctly clearing dirty bits in d cache.
 2021-10-25 14:07:44 -05:00
David Harris
14e6d2c576 Converted flops to synchronous reset now that reset signal is synchronized 2021-10-25 11:49:20 -07:00
David Harris
47124f36c8 Added synchronizer to reset 2021-10-25 10:05:41 -07:00
Ross Thompson
ebef47b1c9 Modified the cache's sram model so if it used to synthesize flip flops it terminates the read critical path at the address's input rather than the output read data. 2021-10-24 21:21:49 -05:00
bbracker
eb9740bc31 manually resolved git merge conflicts in testbench linux after checkpointing 2021-10-24 15:02:19 -07:00
Ross Thompson
87aaec3b6c Partial cleanup of unused signals in caches and bpred. 2021-10-24 15:04:20 -05:00
bbracker
dcd4d9dd9f add checkpointing to linux testbench 2021-10-24 06:47:35 -07:00
David Harris
106982e493 more lsu/ifu lint cleanup 2021-10-23 12:10:13 -07:00
David Harris
8b1dc81d34 more lsu/ifu lint cleanup 2021-10-23 12:00:32 -07:00
David Harris
88b2d9e687 lsu/ifu lint cleanup 2021-10-23 11:41:20 -07:00
David Harris
d0aa6911ff random lint cleanup 2021-10-23 11:24:36 -07:00
David Harris
bb4ad264ce IEU cleanup 2021-10-23 11:13:28 -07:00
David Harris
b6bb33ecef lint cleanup 2021-10-23 11:03:28 -07:00
David Harris
5e961973cb IEU lint cleanup 2021-10-23 10:51:53 -07:00
David Harris
708b914a65 Lint cleanup from wallypipeliendhart 2021-10-23 10:29:52 -07:00
David Harris
817795f619 Lint cleanup: ahblite, ifu, hart 2021-10-23 10:12:33 -07:00
David Harris
2abec36221 Lint cleanup 2021-10-23 09:58:52 -07:00
David Harris
6ae9aa7d80 lint cleanup: FPU and privileged 2021-10-23 09:41:24 -07:00
David Harris
80d2b9bc0d subword read and csrc lint cleanup 2021-10-23 09:29:15 -07:00
David Harris
0eabd0ecc2 FMA and CSRC lint cleanup 2021-10-23 09:20:24 -07:00
David Harris
5235e61d9e Lint cleanup 2021-10-23 09:06:21 -07:00
David Harris
bf3eb7b814 update scripts for handling src/*/* subdirectories 2021-10-23 08:54:29 -07:00
David Harris
7732d38c36 lint cleaning and moved files into subdirectories 2021-10-23 08:53:32 -07:00
David Harris
ff409d4fe7 Lint cleanup 2021-10-23 08:39:21 -07:00
David Harris
8b854bb1c2 Cleaned up LINT erors 2021-10-23 06:28:49 -07:00
David Harris
5142bfd624 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-10-23 06:15:49 -07:00
David Harris
3407b63c8a Added -lint flag to vsim. Cleaned some lint errors. Moved lint-wally to regression directory for convenience. 2021-10-23 06:15:26 -07:00
Ross Thompson
6bad4058eb Merge branch 'main' into fpga 2021-10-22 16:09:16 -05:00