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Updated IFU variable naming for clarity

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Noah Limpert 2021-11-17 12:39:05 -08:00
parent 3f76549a7d
commit 832b23b8a4
1 changed files with 31 additions and 16 deletions
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47
wally-pipelined/src/wally/wallypipelinedhart.sv
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@ -155,26 +155,41 @@ module wallypipelinedhart (
ifu ifu(
.clk, .reset,
.StallF, .StallD, .StallE, .StallM, .StallW,
.FlushF, .FlushD, .FlushE, .FlushM, .FlushW,
.InstrInF(InstrRData), .InstrAckF, .PCF, .InstrPAdrF, .InstrReadF, .ICacheStallF,
.clk, .reset,
.StallF, .StallD, .StallE, .StallM, .StallW,
.FlushF, .FlushD, .FlushE, .FlushM, .FlushW,
// Fetch
.InstrInF(InstrRData), .InstrAckF, .PCF, .InstrPAdrF,
.InstrReadF, .ICacheStallF,
// Execute
.PCLinkE, .PCSrcE, .PCTargetE, .PCE,
.BPPredWrongE,
.RetM, .TrapM,
.PrivilegedNextPCM, .InvalidateICacheM,
.InstrD, .InstrM,
.PCM, .InstrClassM,
.BPPredDirWrongM,.BTBPredPCWrongM,.RASPredPCWrongM, .BPPredClassNonCFIWrongM,
.IllegalBaseInstrFaultD, .ITLBInstrPageFaultF, .IllegalIEUInstrFaultD,
.InstrMisalignedFaultM, .InstrMisalignedAdrM,
// Mem
.RetM, .TrapM, .PrivilegedNextPCM, .InvalidateICacheM,
.InstrD, .InstrM, . PCM, .InstrClassM, .BPPredDirWrongM,
.BTBPredPCWrongM, .RASPredPCWrongM, .BPPredClassNonCFIWrongM,
// Writeback
// output logic
// Faults
.IllegalBaseInstrFaultD, .ITLBInstrPageFaultF,
.IllegalIEUInstrFaultD, .InstrMisalignedFaultM,
.InstrMisalignedAdrM,
// mmu management
.PrivilegeModeW, .PTE, .PageType, .SATP_REGW,
.STATUS_MXR, .STATUS_SUM, .STATUS_MPRV, .STATUS_MPP,
.ITLBWriteF, .ITLBFlushF,
.WalkerInstrPageFaultF,
.ITLBMissF,
.PMPCFG_ARRAY_REGW, .PMPADDR_ARRAY_REGW,
.STATUS_MXR, .STATUS_SUM, .STATUS_MPRV,
.STATUS_MPP, .ITLBWriteF, .ITLBFlushF,
.WalkerInstrPageFaultF, .ITLBMissF,
// pmp/pma (inside mmu) signals. *** temporarily from AHB bus but eventually replace with internal versions pre H
.PMPCFG_ARRAY_REGW, .PMPADDR_ARRAY_REGW,
.InstrAccessFaultF
); // instruction fetch unit: PC, branch prediction, instruction cache