cvw/wally-pipelined/src
2021-12-14 14:46:29 -06:00
..
cache Cleaned up fpga synthesis script. 2021-12-13 18:26:54 -06:00
ebu Simplified ALU and source multiplexers pass tests 2021-12-13 07:57:38 -08:00
fpu Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-12-08 13:48:49 -08:00
generic Merge branch 'main' into fpga 2021-11-29 10:06:53 -06:00
hazard Added proper credit to Richard Davis, the author of the original sd card reader. 2021-12-12 15:05:50 -06:00
ieu ALU and datapath cleanup 2021-12-14 11:15:47 -08:00
ifu Comments for dcache and icache refactoring. 2021-12-14 14:46:29 -06:00
lsu Comments for dcache and icache refactoring. 2021-12-14 14:46:29 -06:00
mmu Merge branch 'main' into fpga 2021-11-29 10:06:53 -06:00
muldiv Removed .* from hazard hzu(.*) in wallypipelinedhart.sv. 2021-11-17 14:08:08 -08:00
privileged priviledge .* removed, passed regression 2021-12-13 00:34:43 -08:00
sdc Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-12-12 17:21:51 -06:00
uncore Cleaned up fpga synthesis script. 2021-12-13 18:26:54 -06:00
wally Refactoring ALU and datapath muxes 2021-12-08 12:33:53 -08:00