cvw/wally-pipelined/src
2021-12-08 14:09:58 -08:00
..
cache Merge branch 'main' into fpga 2021-11-29 10:06:53 -06:00
ebu Lint cleanup: ahblite, ifu, hart 2021-10-23 10:12:33 -07:00
fpu updated fcmp.sv instantiation to remove x*'s 2021-12-08 13:34:33 -08:00
generic Merge branch 'main' into fpga 2021-11-29 10:06:53 -06:00
hazard IEU cleanup 2021-10-23 11:13:28 -07:00
ieu removed .* instantiation from ieu.sv and datapth.sv in ieu folder 2021-12-08 00:24:27 -08:00
ifu .* resolved in ifu.sv 2021-12-02 10:32:35 -08:00
lsu Removed .* from mmu instance inside lsu.sv. 2021-12-08 00:15:30 -08:00
mmu Merge branch 'main' into fpga 2021-11-29 10:06:53 -06:00
muldiv Removed .* from hazard hzu(.*) in wallypipelinedhart.sv. 2021-11-17 14:08:08 -08:00
privileged Merge branch 'main' into fpga 2021-11-29 10:06:53 -06:00
sdc Fixed some issues with the SDC having a different counter. When this is copied into synthesis the file names where the same and it gave a conflict. 2021-12-08 15:50:15 -06:00
uncore Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-12-08 14:09:58 -08:00
wally Merge branch 'main' into fpga 2021-11-29 10:10:37 -06:00