Synchronous reset in non-flop blocks

wally-pipelined/src/cache/cacheway.sv

@@ -104,11 +104,9 @@ module cacheway #(parameter NUMLINES=512, parameter BLOCKLEN = 256, TAGLEN = 26,
     
   
   always_ff @(posedge clk, posedge reset) begin
-    if (reset) 
-  	ValidBits <= {NUMLINES{1'b0}};
-    else if (InvalidateAll) 
-  	ValidBits <= {NUMLINES{1'b0}};
-    else if (SetValid & (WriteEnable | VDWriteEnable)) ValidBits[WAdr] <= 1'b1;
+    if (reset)                                           ValidBits <= {NUMLINES{1'b0}};
+    else if (InvalidateAll)                              ValidBits <= {NUMLINES{1'b0}};
+    else if (SetValid & (WriteEnable | VDWriteEnable))   ValidBits[WAdr] <= 1'b1;
     else if (ClearValid & (WriteEnable | VDWriteEnable)) ValidBits[WAdr] <= 1'b0;
   end
 
@@ -118,7 +116,6 @@ module cacheway #(parameter NUMLINES=512, parameter BLOCKLEN = 256, TAGLEN = 26,
 
   generate
     if(DIRTY_BITS) begin
-
       always_ff @(posedge clk, posedge reset) begin
 	if (reset) 
   	  DirtyBits <= {NUMLINES{1'b0}};

wally-pipelined/src/fpu/fregfile.sv

@@ -39,7 +39,7 @@ module fregfile (
    // write fourth port on rising edge of clock (A4/WD4/WE4)
    // write occurs on falling edge of clock   
    
-   always_ff @(negedge clk or posedge reset)
+   always_ff @(negedge clk) // or posedge reset)
      if (reset) for(i=0; i<32; i++) rf[i] <= 0;
      else if (we4) rf[a4] <= wd4;	
    

wally-pipelined/src/ieu/regfile.sv

@@ -43,7 +43,7 @@ module regfile (
   
   // reset is intended for simulation only, not synthesis
     
-  always_ff @(negedge clk or posedge reset)
+  always_ff @(negedge clk) // or posedge reset)
     if (reset) for(i=1; i<32; i++) rf[i] <= 0;
     else if (we3) rf[a3] <= wd3;	
 

wally-pipelined/src/privileged/csrc.sv

@@ -149,7 +149,7 @@ module csrc #(parameter
         for (i = 3; i < `COUNTERS; i = i+1) begin
             assign WriteHPMCOUNTERM[i] = CSRMWriteM && (CSRAdrM == MHPMCOUNTERBASE + i);
             assign NextHPMCOUNTERM[i][`XLEN-1:0] = WriteHPMCOUNTERM[i] ? CSRWriteValM : HPMCOUNTERPlusM[i][`XLEN-1:0];
-            always @(posedge clk, posedge reset) // ModelSim doesn't like syntax of passing array element to flop
+            always @(posedge clk) //, posedge reset) // ModelSim doesn't like syntax of passing array element to flop
               if (reset) HPMCOUNTER_REGW[i][`XLEN-1:0] <= #1 0;
               else if (~StallW) HPMCOUNTER_REGW[i][`XLEN-1:0] <= #1 NextHPMCOUNTERM[i];
 
@@ -159,7 +159,7 @@ module csrc #(parameter
                 assign HPMCOUNTERPlusM[i] = {HPMCOUNTERH_REGW[i], HPMCOUNTER_REGW[i]} + {63'b0, CounterEvent[i] & ~MCOUNTINHIBIT_REGW[i]};
                 assign WriteHPMCOUNTERHM[i] = CSRMWriteM && (CSRAdrM == MHPMCOUNTERHBASE + i);
                 assign NextHPMCOUNTERHM[i] = WriteHPMCOUNTERHM[i] ? CSRWriteValM : HPMCOUNTERPlusM[i][63:32];
-                always @(posedge clk, posedge reset) // ModelSim doesn't like syntax of passing array element to flop
+                always @(posedge clk) //, posedge reset) // ModelSim doesn't like syntax of passing array element to flop
                     if (reset) HPMCOUNTERH_REGW[i][`XLEN-1:0] <= #1 0;
                     else if (~StallW) HPMCOUNTERH_REGW[i][`XLEN-1:0] <= #1 NextHPMCOUNTERHM[i];
             end else begin

wally-pipelined/src/privileged/csri.sv

@@ -78,19 +78,17 @@ module csri #(parameter
       assign MIP_WRITE_MASK = 12'h000;
       assign SIP_WRITE_MASK = 12'h000;
     end
-    always @(posedge clk, posedge reset) begin // *** I strongly feel that IntInM should go directly to IP_REGW -- Ben 9/7/21
+    always @(posedge clk) //, posedge reset) begin // *** I strongly feel that IntInM should go directly to IP_REGW -- Ben 9/7/21
       if (reset)          IP_REGW_writeable <= 10'b0;
       else if (WriteMIPM) IP_REGW_writeable <= (CSRWriteValM[9:0] & MIP_WRITE_MASK[9:0]) | IntInM[9:0]; // MTIP unclearable
       else if (WriteSIPM) IP_REGW_writeable <= (CSRWriteValM[9:0] & SIP_WRITE_MASK[9:0]) | IntInM[9:0]; // MTIP unclearable
 //      else if (WriteUIPM) IP_REGW = (CSRWriteValM & 12'hBBB) | (NextIPM & 12'h080); // MTIP unclearable
       else                IP_REGW_writeable <= IP_REGW_writeable | IntInM[9:0]; // *** check this turns off interrupts properly even when MIDELEG changes
-    end
-    always @(posedge clk, posedge reset) begin
+    always @(posedge clk) //, posedge reset) begin
       if (reset)          IE_REGW <= 12'b0;
       else if (WriteMIEM) IE_REGW <= (CSRWriteValM[11:0] & 12'hAAA); // MIE controls M and S fields
       else if (WriteSIEM) IE_REGW <= (CSRWriteValM[11:0] & 12'h222) | (IE_REGW & 12'h888); // only S fields
 //      else if (WriteUIEM) IE_REGW = (CSRWriteValM & 12'h111) | (IE_REGW & 12'hAAA); // only U field
-    end
   endgenerate
 
   // restricted views of registers

wally-pipelined/src/privileged/csrsr.sv

@@ -108,7 +108,7 @@ module csrsr (
 
   // registers for STATUS bits
   // complex register with reset, write enable, and the ability to update other bits in certain cases
-  always_ff @(posedge clk, posedge reset)
+  always_ff @(posedge clk) //, posedge reset)
     if (reset) begin
       STATUS_TSR_INT <= #1 0;
       STATUS_TW_INT <= #1 0;