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Made abhlite instation on wallypipehart more clear, updated spacing for consistency

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This commit is contained in:
Noah Limpert 2021-11-24 22:48:01 -08:00
parent 8a64510ee4
commit 0cd31bfc1f
1 changed files with 36 additions and 37 deletions
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73
wally-pipelined/src/wally/wallypipelinedhart.sv
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@ -276,50 +276,49 @@ module wallypipelinedhart (
ahblite ebu(// IFU connections
.InstrPAdrF(InstrPAdrF),
.InstrReadF(InstrReadF),
.InstrRData(InstrRData),
.InstrAckF(InstrAckF),
// LSU connections
.DCtoAHBPAdrM(DCtoAHBPAdrM), // rename to DCtoAHBPAdrM
.DCtoAHBReadM(DCtoAHBReadM), // rename to DCtoAHBReadM
.DCtoAHBWriteM(DCtoAHBWriteM), // rename to DCtoAHBWriteM
.DCtoAHBWriteData(DCtoAHBWriteData),
.DCfromAHBReadData(DCfromAHBReadData),
.DCfromAHBAck(DCfromAHBAck),
// remove these
.MemSizeM(DCtoAHBSizeM[1:0]), // *** depends on XLEN should be removed
.UnsignedLoadM(1'b0),
.AtomicMaskedM(2'b00),
.*);
.clk, .reset,
.UnsignedLoadM(1'b0), .AtomicMaskedM(2'b00),
.InstrPAdrF, // *** rename these to match block diagram
.InstrReadF, .InstrRData, .InstrAckF,
// Signals from Data Cache
.DCtoAHBPAdrM, .DCtoAHBReadM, .DCtoAHBWriteM, .DCtoAHBWriteData,
.DCfromAHBReadData,
.MemSizeM(DCtoAHBSizeM[1:0]), // *** remove
.DCfromAHBAck,
.HRDATA, .HREADY, .HRESP, .HCLK, .HRESETn,
.HADDR, .HWDATA, .HWRITE, .HSIZE, .HBURST,
.HPROT, .HTRANS, .HMASTLOCK, .HADDRD, .HSIZED,
.HWRITED);
muldiv mdu(
.clk, .reset,
// Execute Stage interface
// .SrcAE, .SrcBE,
.ForwardedSrcAE, .ForwardedSrcBE, // *** these are the src outputs before the mux choosing between them and PCE to put in srcA/B
.Funct3E, .Funct3M,
.MulDivE, .W64E,
// Writeback stage
.MulDivResultW,
// Divide Done
.DivBusyE,
// hazards
.StallM, .StallW, .FlushM, .FlushW
// Execute Stage interface
// .SrcAE, .SrcBE,
.ForwardedSrcAE, .ForwardedSrcBE, // *** these are the src outputs before the mux choosing between them and PCE to put in srcA/B
.Funct3E, .Funct3M,
.MulDivE, .W64E,
// Writeback stage
.MulDivResultW,
// Divide Done
.DivBusyE,
// hazards
.StallM, .StallW, .FlushM, .FlushW
); // multiply and divide unit
hazard hzu(
.BPPredWrongE, .CSRWritePendingDEM, .RetM, .TrapM,
.LoadStallD, .StoreStallD, .MulDivStallD, .CSRRdStallD,
.LSUStall, .ICacheStallF,
.FPUStallD, .FStallD,
.DivBusyE, .FDivBusyE,
.EcallFaultM, .BreakpointFaultM,
.InvalidateICacheM,
// Stall & flush outputs
.StallF, .StallD, .StallE, .StallM, .StallW,
.FlushF, .FlushD, .FlushE, .FlushM, .FlushW); // global stall and flush control
.BPPredWrongE, .CSRWritePendingDEM, .RetM, .TrapM,
.LoadStallD, .StoreStallD, .MulDivStallD, .CSRRdStallD,
.LSUStall, .ICacheStallF,
.FPUStallD, .FStallD,
.DivBusyE, .FDivBusyE,
.EcallFaultM, .BreakpointFaultM,
.InvalidateICacheM,
// Stall & flush outputs
.StallF, .StallD, .StallE, .StallM, .StallW,
.FlushF, .FlushD, .FlushE, .FlushM, .FlushW
); // global stall and flush control
// Priveleged block operates in M and W stages, handling CSRs and exceptions
privileged priv(.*);