Ross Thompson
4db017dac3
Possible fix for ifu/lsu arbiration issue.
2022-09-27 17:24:35 -05:00
Ross Thompson
4062fe56c0
Possible fix to the bus cache interaction.
2022-09-27 11:34:33 -05:00
Ross Thompson
07bb11518e
Found a hidden bug in the cache to bus fsm interlock.
2022-09-26 17:41:30 -05:00
Ross Thompson
996c4ca8f2
renamed ahbmulticontroller to ebu.
2022-09-26 14:37:18 -05:00
Ross Thompson
8ed173a5f5
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-09-26 12:49:16 -05:00
Ross Thompson
0fcc314d06
Yesterday David and I found what is likely a bug in our AHB implementation. HTRANS was getting reset to 2 rather than 0 at the end of a burst transaction. This is fixed.
2022-09-26 12:48:26 -05:00
David Harris
713df785d1
changed always_ff to always in sram1p1rw to fix testbench complaint
2022-09-25 19:56:40 -07:00
Ross Thompson
38edbde966
Renamed RW signals through the caches, bus interfaces, and IFU/LSU.
...
CPU to $ is called LSURWM or IFURWF.
CPU to Bus is called BusRW
$ to Bus is called CacheBusRW.
2022-09-23 11:46:53 -05:00
Ross Thompson
2eaf3af6c7
Removed the write first sram model.
2022-09-22 16:12:08 -05:00
Ross Thompson
cec50ce208
The valid and dirty bits match the SRAM implementation now.
2022-09-22 16:09:09 -05:00
Ross Thompson
b48d6b5e1f
Solved the sram write first / read first issue. Works correctly with read first now.
2022-09-22 14:16:26 -05:00
Ross Thompson
89e6ddfa4e
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-09-21 18:24:06 -05:00
Ross Thompson
99e01dd31f
Cleaned up the IFU and LSU around dtim and irom address calculation.
2022-09-21 18:23:56 -05:00
David Harris
d6297a2f2e
For radix 4 division, fixed initial C and then could remove unexplained shift from divshiftcalc
2022-09-21 13:30:35 -07:00
David Harris
46680b80a7
Eliminated store after store stall when no cache; simplified divshiftcalc logic.
2022-09-21 13:02:34 -07:00
Ross Thompson
f57b0b9950
Updated IROMAdr logic.
2022-09-21 12:42:43 -05:00
Ross Thompson
0add170b44
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-09-21 12:36:52 -05:00
Ross Thompson
3fb0a13fe2
Moved other SRAMs to generic/mem.
2022-09-21 12:36:03 -05:00
David Harris
030fb79a3c
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-09-21 10:35:11 -07:00
David Harris
cb4c3ff1ce
Simplified shipping in divshiftcalc; enhanced testbench-fp to be able to run all 32-bit tests generated by sqrttest
2022-09-21 10:35:08 -07:00
Ross Thompson
66c45949b5
Renamed brom1p1r to rom1p1r.
...
removed used file bram2p1r1w.sv.
2022-09-21 12:31:20 -05:00
Ross Thompson
832658838d
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-09-21 12:20:12 -05:00
Ross Thompson
ac864a6ca3
Merged together bram1p1rw with sram1p1rw as sram1p1rw.
...
Fixed a major issue with the real SRAM implemenation.
2022-09-21 12:20:00 -05:00
Ross Thompson
c0884ecc63
Modified sram1p1rw to support 3 different implementation styles.
...
SRAM, Read first, and Write first.
2022-09-21 11:26:00 -05:00
David Harris
129b9343fe
commented SpecialCase
2022-09-21 05:02:08 -07:00
David Harris
5e1932c649
Added SpecialCaseReg to hold SpecialCase for fdivsqrtpostproc
2022-09-21 04:55:43 -07:00
David Harris
f7d272c315
Gated sticky bit in fdiv with SpecialCase
2022-09-20 20:05:00 -07:00
David Harris
3b98881c4e
renamed u to udigit to avoid conflict with U
2022-09-20 19:29:23 -07:00
cturek
6e300a667e
Fixed R4 Sqrt overshifting
2022-09-21 00:05:36 +00:00
cturek
c3c764f0ba
Fixed fgen4
2022-09-20 20:00:01 +00:00
Ross Thompson
980b35d585
Merge branch 'tempMain' into main
2022-09-20 13:57:38 -05:00
Ross Thompson
426ec6222b
Added chip enables to sram.
2022-09-20 10:49:14 -05:00
Ross Thompson
822d989383
Added comment.
2022-09-20 09:49:53 -05:00
Ross Thompson
4c3c517322
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-09-20 09:47:16 -05:00
David Harris
00c15ec472
renamed q to u for unified digit selection
2022-09-20 04:35:14 -07:00
David Harris
d01588d693
Removed D2 and D2b from radix2 stage
2022-09-20 04:20:38 -07:00
David Harris
2ea7df1b6d
Simplified UM initialization
2022-09-20 04:18:12 -07:00
David Harris
0d5e80a4f0
fdivsqrtfgen4 comments
2022-09-20 04:13:21 -07:00
David Harris
653c458241
Moved fpu modules into subdirectories
2022-09-20 04:12:05 -07:00
David Harris
0ec1886b89
Partitioned fdivsqrt into one module per file and added file names to opening comments
2022-09-20 03:57:57 -07:00
David Harris
a05b6486b1
Simplified fdivsqrtpostproc QmM logic
2022-09-20 03:30:18 -07:00
David Harris
87cde2c427
make QmM size b+1 indpenedent of radix
2022-09-20 03:25:09 -07:00
David Harris
e455f41b97
clean up divshiftcalc
2022-09-20 03:19:50 -07:00
David Harris
211705eca2
clean up divshiftcalc
2022-09-20 03:17:29 -07:00
David Harris
d3b2a192eb
clean up divshiftcalc
2022-09-20 03:13:11 -07:00
David Harris
f5083803c2
clean up divshiftcalc
2022-09-20 03:08:25 -07:00
David Harris
2faa0d14be
Cleaning up divshiftcalc LOGNORMSHIFTSZ
2022-09-20 02:35:01 -07:00
Jacob Pease
1e7bbe1a87
Fixed rxfifotimeout restarting for every new character, even when already high.
2022-09-19 18:00:30 -05:00
cturek
019a6eb9f5
Radix 4 sqrt passing first two tests
2022-09-19 21:26:32 +00:00
Ross Thompson
bcca9a62c5
Fixed up IFU ahb interface names and widths.
2022-09-19 10:54:22 -05:00
David Harris
8e90862dad
Removed EarlyTermShift from fdiv
2022-09-19 08:44:23 -07:00
David Harris
73ceb4590c
Finished unified divsqrt otfc and fgen name changes
2022-09-19 08:30:59 -07:00
David Harris
3cf6becaf4
fdivsqrtiter simplification
2022-09-19 01:08:01 -07:00
David Harris
e840edc4e6
Reduced number of cycles needed for division
2022-09-19 01:02:04 -07:00
David Harris
d6f1453275
Cleaned up otfc4
2022-09-19 00:58:20 -07:00
David Harris
309995a6e9
OTFC simplification
2022-09-19 00:51:56 -07:00
David Harris
59b6346a28
Removed unused otfc for Q
2022-09-19 00:43:27 -07:00
David Harris
e764d4322c
fdiv cleanup
2022-09-19 00:32:34 -07:00
David Harris
cf0c20d489
Division working again for radix 2 with unified OTFC
2022-09-19 00:30:30 -07:00
David Harris
b636072914
Unified on-the-fly conversion working for radix 2; broke radix-4 division
2022-09-19 00:04:00 -07:00
David Harris
4dbe1035cb
Added 2 bits to C to initialize properly
2022-09-18 22:44:22 -07:00
David Harris
f202eb0f6f
Added 2 bits to C to initialize properly
2022-09-18 22:42:35 -07:00
Ross Thompson
57c366c1b2
Removed NonIROM and NonDTIM select signals from IFU and LSU.
2022-09-17 22:01:03 -05:00
Ross Thompson
cb34b7c98f
Found the ahb burst bug.
...
We had instruction fetches fixed HSIZE = 2 (4 bytes) for all requests. It should be HSIZE = 3 (8 bytes) for cache fetches and 4 for uncached reads. The reason this worked for non burst is the DDR4 memory controller returns the full double word even for 4 byte reads. In burst mode the second beat ending up pointing to the next 4 bytes rather than the next 8 bytes.
2022-09-17 20:30:01 -05:00
David Harris
b74a68ff0f
Reduced number of cycles required for lower-precision sqrt
2022-09-17 09:55:34 -07:00
David Harris
ac78823f6c
Starting to adust number of cycles for division/sqrt
2022-09-17 05:58:59 -07:00
cturek
79addec27a
Fixed j1 to align with new C reg
2022-09-16 02:15:48 +00:00
David Harris
8f2b3b2387
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-09-15 12:49:21 -07:00
David Harris
94dca9194e
renamed endianswap
2022-09-15 12:49:18 -07:00
Ross Thompson
38e114a6c0
Fixed subword read to work with bigendian.
2022-09-15 14:08:04 -05:00
David Harris
29d9ded25c
FDIVSQRT cleanup
2022-09-15 09:10:57 -07:00
Ross Thompson
cea012a640
renamed multimanager to multicontroller.
2022-09-14 14:03:37 -05:00
Ross Thompson
bf6468a24c
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-09-14 13:59:22 -05:00
cturek
da67e02392
Added shift for radix 4 sqrt
2022-09-14 17:34:24 +00:00
cturek
47d02db2eb
Moved X-1 to preproc
2022-09-14 17:26:56 +00:00
cturek
4f3baea0fc
removed unnecessary XZero from wsmux
2022-09-14 16:59:52 +00:00
David Harris
14bbd07e63
ZMerge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-09-14 09:42:17 -07:00
Ross Thompson
2c86badeb2
pipelining of fetch into evict AHB requests.
2022-09-13 17:51:55 -05:00
Ross Thompson
c7d3580637
Renamed signals in the LSU.
2022-09-13 11:47:39 -05:00
David Harris
1495305045
Removed unused signals
2022-09-12 11:35:35 -07:00
David Harris
7197a6de44
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-09-08 16:05:58 -07:00
David Harris
7639c05e51
Moved C to shift before rather than after using in an iteration
2022-09-08 16:05:53 -07:00
David Harris
7ba9b0b349
divsqrt comment cleanup
2022-09-08 15:40:42 -07:00
Ross Thompson
c4a7d3c147
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-09-08 17:15:46 -05:00
David Harris
5ea82cff33
CSA-based completion detection
2022-09-08 14:58:08 -07:00
Ross Thompson
7f1ae039b0
Optimization. Able to remove hptw address muxes from the E stage.
2022-09-08 15:51:18 -05:00
Ross Thompson
0904951a8c
Oups the ahbinterface.sv was accidentally named abhinterface.sv.
2022-09-08 13:21:37 -05:00
Ross Thompson
6e8d97e921
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-09-07 16:36:51 -05:00
Ross Thompson
f4e3036593
Oups fixed order of ending swap with mux between cache and fetch buffer.
2022-09-07 16:29:47 -05:00
David Harris
2d5e7827df
Factored out aplusbeq0 unit
2022-09-07 11:36:35 -07:00
David Harris
838d98cf4b
Preprocessing cleanup
2022-09-07 10:21:27 -07:00
Ross Thompson
5a0cda9860
Merge branch 'multimanager' into main
2022-09-07 10:54:27 -05:00
David Harris
c8e0ea067e
Continued simplifying fdivsqrt postprocessing
2022-09-07 07:02:22 -07:00
David Harris
b0ff3a0952
Continued simplifying fdivsqrt postprocessing
2022-09-07 07:00:13 -07:00
David Harris
9e7926e8d7
Moving postprocessing into postproc block
2022-09-07 06:42:37 -07:00
David Harris
c39e71f168
fdivsqrtfsm cleanup
2022-09-07 06:32:07 -07:00
David Harris
027b303b20
fdivsqrtfsm cleanup
2022-09-07 06:27:01 -07:00
David Harris
19e449b83d
Fixed regression for divsqrt radix2
2022-09-07 06:12:23 -07:00
Ross Thompson
7ad7cea25b
James found a bug in synchronizer. Was not actually back to back flip flops.
2022-09-06 15:06:54 -05:00
Ross Thompson
bc15f6c5e4
Added logic to make burst optional.
2022-09-06 09:21:21 -05:00
