Ross Thompson
775309165b
Small cleanup of interlockfsm.
2022-10-22 16:29:51 -05:00
Ross Thompson
6696624971
comment updates.
2022-10-22 16:28:44 -05:00
Ross Thompson
12c5525807
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-10-22 16:27:30 -05:00
Ross Thompson
4db912678d
Changed FDivBusyE to stall the whole pipeline. Any instruction in the Executation which depended on the output of an instruction in the writeback stage would be lost if the back end of the pipelined advanced. The solution is to stall the whole pipeline.
2022-10-22 16:27:20 -05:00
Jacob Pease
b1170ec7a2
Extended rxfifotimeout count to actually be 4 characters long.
2022-10-20 17:35:49 -05:00
Ross Thompson
2c5847b01f
Moving interlockfsm changes to a temporary branch.
...
reduced complexity of cache mux controls.
2022-10-19 15:08:23 -05:00
Ross Thompson
9cadd4c6ec
Broken don't use this state.
2022-10-19 14:31:22 -05:00
Ross Thompson
c6a9b17918
Noted possible bug with endianness during hptw.
...
Minor complexity reduction in interlockfsm. I think there is a lot of room to simplify.
2022-10-19 12:20:19 -05:00
Ross Thompson
d4c5440f25
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-10-18 15:06:09 -05:00
Ross Thompson
92accfb1a6
Updated uart settings and fpga wave config.
2022-10-18 15:05:33 -05:00
Ross Thompson
47608df73e
Possible fix for interrupt during a floating point divide.
2022-10-18 15:04:21 -05:00
Ross Thompson
65c2fe294a
Merged cacheable with seluncachedadr.
2022-10-17 13:29:21 -05:00
amaiuolo
56455bb9ad
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally
2022-10-13 22:36:57 +00:00
amaiuolo
1ae48e0edc
added amaiuolo@hmc.edu
2022-10-13 22:36:52 +00:00
Ross Thompson
22603464ae
Fixed uncached read bug introduced by yesterday's changes.
2022-10-13 11:11:36 -05:00
Ross Thompson
a4390dd07f
Fixed LSU to correctly handle the difference between LLEN and AHBW.
2022-10-12 12:06:15 -05:00
Ross Thompson
b79872180b
Actually fixed the bus width issue coming out of the cache.
...
The root cause is the ahb bus width can be different from LLEN.
If we switch the d-cache to outputing LLEN and on LLEN intervals, subword read needs to operate on LLEN as well.
Then the cache always outputs LLEN data which may need to be muxed down into 2 or more subwords if ABHW is smaller than LLEN.
2022-10-12 11:33:10 -05:00
Kip Macsai-Goren
1dd9cb6697
quick fix to endianness wapping 64 bit reads in 32 bit confgs
2022-10-11 23:08:02 +00:00
Ross Thompson
7ddcf38fa9
Modified LSU to support DTIM without CSRs.
2022-10-11 14:05:20 -05:00
Ross Thompson
77de96905a
Fixed first problem with the rv64i IROM.
2022-10-11 11:35:40 -05:00
David Harris
cc9a2fc62d
Removed imperas tests from rv32i/rv64i because the configs lack privileged support expected in the tests. Also cleaned up comment in LSU
2022-10-10 10:22:12 -07:00
David Harris
31e9af0eb2
Made simple RV64 configuration be RV64i. Eliminated rv64ic and rv64fp. Fixed some bugs related to new width
2022-10-10 09:10:55 -07:00
David Harris
fde4832642
Removed unnecessary configuration conditions from subwordread sign extension/NaN boxing
2022-10-10 07:12:37 -07:00
David Harris
04dc0ac02c
New fdivsqrtqsel4cmp module based on comparators rather than table lookup
2022-10-09 04:47:44 -07:00
David Harris
4f312ea2e7
Moved shift into divsqrt stage and cleaned up comments
2022-10-09 04:45:45 -07:00
David Harris
2aa43848f5
fdivsqrt code cleanup
2022-10-09 03:37:27 -07:00
Ross Thompson
6ff4abd4f7
Cleaned up the new muxes to select between IROM/ICACHE/BUS and DTIM/DCACHE/BUS.
2022-10-05 15:46:53 -05:00
Ross Thompson
28584e4cca
Fixed wally32e.
2022-10-05 15:37:01 -05:00
Ross Thompson
52a1d3dafe
Name clarifications.
2022-10-05 15:36:56 -05:00
Ross Thompson
aa09b1ef16
Fixed bug with combined dtim+bus.
2022-10-05 15:16:01 -05:00
Ross Thompson
98521d073f
Possibly have working dtim + bus config.
2022-10-05 15:08:20 -05:00
Ross Thompson
bf6f0e7219
Fixed bug in EBU.
2022-10-05 14:51:12 -05:00
Ross Thompson
cabcb5e89e
Modified the LSU and IFU to allow concurrent DTIM/DCACHE+BUS and IROM/ICACHE+BUS.
...
Don't use this commit as the rv32i tests are not passing.
2022-10-05 14:51:02 -05:00
Ross Thompson
ea70e1c598
Optimized the ebu's beat counting.
2022-10-05 10:58:23 -05:00
Ross Thompson
294645a49f
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-10-04 17:38:49 -05:00
Ross Thompson
494f8b94f4
Reordered the eviction and fetch in cache so it follows a more logical order.
2022-10-04 17:36:07 -05:00
Ross Thompson
18e739befc
Modified cache lru to not have the delayed write.
2022-10-04 15:14:58 -05:00
Kip Macsai-Goren
3f6d05f7a2
addded renamed file
2022-10-04 17:37:05 +00:00
Kip Macsai-Goren
9a0b98037b
Merge branch 'main' of github.com:davidharrishmc/riscv-wally
2022-10-04 17:33:54 +00:00
Kip Macsai-Goren
fb464b9546
Renamed endianswap to match module name
2022-10-04 17:33:49 +00:00
Ross Thompson
0ed0c18aa1
Fixed a very subtle bug in the trap handler. It was possible to select the wrong cause if an interrupt was pending, but it was supressed by Committed and another exception triggered.
2022-10-02 16:21:21 -05:00
Ross Thompson
d08c29e3c5
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-10-01 15:01:22 -05:00
Ross Thompson
41ab4850e1
Disable IFU bus access on TrapM.
2022-10-01 14:54:16 -05:00
Ross Thompson
e27fcb1577
Added logic to not implement the save/restore muxes for LSU in the EBU's controller input stage.
2022-09-29 18:37:34 -05:00
David Harris
657f16dfd1
Adding start signals for integer divider to fdivsqrt
2022-09-29 16:30:25 -07:00
Ross Thompson
2c0132aa9c
Renamed signals in EBU.
2022-09-29 18:29:38 -05:00
cturek
e8a869e0e7
Added integer inputs and flags to divsqrt
2022-09-29 23:08:27 +00:00
Ross Thompson
58d597b614
Simplification to EBU.
2022-09-29 18:06:34 -05:00
Ross Thompson
d81af3bca8
Fixed HTRANS not changing after accepting HREADY. This exposed a bug in uncore.
2022-09-29 11:54:03 -05:00
Ross Thompson
32449dfe97
Hmm. the icache and ifu didn't have a CommittedF signals going back to the privileged unit. They probably should. If an interrupt occurred during the middle of an instruction fetch icache miss I think it would corrupt the icache.
2022-09-28 17:39:51 -05:00
