cvw/pipelined/src
2022-09-21 13:02:34 -07:00
..
cache Moved other SRAMs to generic/mem. 2022-09-21 12:36:03 -05:00
ebu Fixed up IFU ahb interface names and widths. 2022-09-19 10:54:22 -05:00
fpu Eliminated store after store stall when no cache; simplified divshiftcalc logic. 2022-09-21 13:02:34 -07:00
generic Moved other SRAMs to generic/mem. 2022-09-21 12:36:03 -05:00
hazard Added comments about planned changes. 2022-08-29 09:48:00 -05:00
ieu Eliminated store after store stall when no cache; simplified divshiftcalc logic. 2022-09-21 13:02:34 -07:00
ifu Updated IROMAdr logic. 2022-09-21 12:42:43 -05:00
lsu Merged together bram1p1rw with sram1p1rw as sram1p1rw. 2022-09-21 12:20:00 -05:00
mmu Created two new pma regions for dtim and irom. 2022-08-28 13:50:50 -05:00
muldiv Clean up unused signals 2022-05-12 14:49:58 +00:00
ppa cleanup, plots for paper 2022-06-15 18:28:36 +00:00
privileged Cleaned up fcvt selection control to IEU and FPUIllegalInst signals 2022-08-23 12:17:19 -07:00
uncore Renamed brom1p1r to rom1p1r. 2022-09-21 12:31:20 -05:00
wally Found the ahb burst bug. 2022-09-17 20:30:01 -05:00
sdc piplined directory cleanup 2022-01-07 12:43:50 +00:00