David Harris ac78823f6c Starting to adust number of cycles for division/sqrt		2022-09-17 05:58:59 -07:00
..
cache	pipelining of fetch into evict AHB requests.	2022-09-13 17:51:55 -05:00
ebu	renamed multimanager to multicontroller.	2022-09-14 14:03:37 -05:00
fpu	Starting to adust number of cycles for division/sqrt	2022-09-17 05:58:59 -07:00
generic	Factored out aplusbeq0 unit	2022-09-07 11:36:35 -07:00
hazard	Added comments about planned changes.	2022-08-29 09:48:00 -05:00
ieu	Modified the lsu/ifu memory configurations.	2022-08-24 12:35:15 -05:00
ifu	Optimization. Able to remove hptw address muxes from the E stage.	2022-09-08 15:51:18 -05:00
lsu	Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main	2022-09-15 12:49:21 -07:00
mmu	Created two new pma regions for dtim and irom.	2022-08-28 13:50:50 -05:00
muldiv	Clean up unused signals	2022-05-12 14:49:58 +00:00
ppa	cleanup, plots for paper	2022-06-15 18:28:36 +00:00
privileged	Cleaned up fcvt selection control to IEU and FPUIllegalInst signals	2022-08-23 12:17:19 -07:00
uncore	Added generate around the longer latency version of the ram_ahb.sv	2022-09-06 09:21:03 -05:00
wally	renamed multimanager to multicontroller.	2022-09-14 14:03:37 -05:00
sdc	piplined directory cleanup	2022-01-07 12:43:50 +00:00