Ross Thompson 4062fe56c0 Possible fix to the bus cache interaction.		2022-09-27 11:34:33 -05:00
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cache	Possible fix to the bus cache interaction.	2022-09-27 11:34:33 -05:00
ebu	Possible fix to the bus cache interaction.	2022-09-27 11:34:33 -05:00
fpu	For radix 4 division, fixed initial C and then could remove unexplained shift from divshiftcalc	2022-09-21 13:30:35 -07:00
generic	changed always_ff to always in sram1p1rw to fix testbench complaint	2022-09-25 19:56:40 -07:00
hazard	Added comments about planned changes.	2022-08-29 09:48:00 -05:00
ieu	Eliminated store after store stall when no cache; simplified divshiftcalc logic.	2022-09-21 13:02:34 -07:00
ifu	Renamed RW signals through the caches, bus interfaces, and IFU/LSU.	2022-09-23 11:46:53 -05:00
lsu	Renamed RW signals through the caches, bus interfaces, and IFU/LSU.	2022-09-23 11:46:53 -05:00
mmu	Created two new pma regions for dtim and irom.	2022-08-28 13:50:50 -05:00
muldiv	Clean up unused signals	2022-05-12 14:49:58 +00:00
ppa	cleanup, plots for paper	2022-06-15 18:28:36 +00:00
privileged	Cleaned up fcvt selection control to IEU and FPUIllegalInst signals	2022-08-23 12:17:19 -07:00
uncore	Renamed brom1p1r to rom1p1r.	2022-09-21 12:31:20 -05:00
wally	renamed ahbmulticontroller to ebu.	2022-09-26 14:37:18 -05:00
sdc	piplined directory cleanup	2022-01-07 12:43:50 +00:00