Github_Repos/cvw
1
0
Fork 1
mirror of https://github.com/openhwgroup/cvw synced 2025-02-02 01:44:41 +00:00
Code Issues Packages Projects Releases Wiki Activity
4,496 Commits 4 Branches 2 Tags 53 MiB
602d191580
Commit Graph

1577 Commits

Author SHA1 Message Date
David Harris
11fb39b373 Define LOGNORMSHIFTSZ 2022-09-20 08:31:57 -07:00
Ross Thompson
822d989383 Added comment. 2022-09-20 09:49:53 -05:00
Ross Thompson
4c3c517322 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-09-20 09:47:16 -05:00
David Harris
00c15ec472 renamed q to u for unified digit selection 2022-09-20 04:35:14 -07:00
David Harris
d01588d693 Removed D2 and D2b from radix2 stage 2022-09-20 04:20:38 -07:00
David Harris
2ea7df1b6d Simplified UM initialization 2022-09-20 04:18:12 -07:00
David Harris
0d5e80a4f0 fdivsqrtfgen4 comments 2022-09-20 04:13:21 -07:00
David Harris
653c458241 Moved fpu modules into subdirectories 2022-09-20 04:12:05 -07:00
David Harris
0ec1886b89 Partitioned fdivsqrt into one module per file and added file names to opening comments 2022-09-20 03:57:57 -07:00
David Harris
a05b6486b1 Simplified fdivsqrtpostproc QmM logic 2022-09-20 03:30:18 -07:00
David Harris
87cde2c427 make QmM size b+1 indpenedent of radix 2022-09-20 03:25:09 -07:00
David Harris
e455f41b97 clean up divshiftcalc 2022-09-20 03:19:50 -07:00
David Harris
211705eca2 clean up divshiftcalc 2022-09-20 03:17:29 -07:00
David Harris
d3b2a192eb clean up divshiftcalc 2022-09-20 03:13:11 -07:00
David Harris
f5083803c2 clean up divshiftcalc 2022-09-20 03:08:25 -07:00
David Harris
2faa0d14be Cleaning up divshiftcalc LOGNORMSHIFTSZ 2022-09-20 02:35:01 -07:00
Jacob Pease
1e7bbe1a87 Fixed rxfifotimeout restarting for every new character, even when already high. 2022-09-19 18:00:30 -05:00
cturek
019a6eb9f5 Radix 4 sqrt passing first two tests 2022-09-19 21:26:32 +00:00
Ross Thompson
bcca9a62c5 Fixed up IFU ahb interface names and widths. 2022-09-19 10:54:22 -05:00
David Harris
8e90862dad Removed EarlyTermShift from fdiv 2022-09-19 08:44:23 -07:00
David Harris
73ceb4590c Finished unified divsqrt otfc and fgen name changes 2022-09-19 08:30:59 -07:00
David Harris
3cf6becaf4 fdivsqrtiter simplification 2022-09-19 01:08:01 -07:00
David Harris
e840edc4e6 Reduced number of cycles needed for division 2022-09-19 01:02:04 -07:00
David Harris
d6f1453275 Cleaned up otfc4 2022-09-19 00:58:20 -07:00
David Harris
309995a6e9 OTFC simplification 2022-09-19 00:51:56 -07:00
David Harris
59b6346a28 Removed unused otfc for Q 2022-09-19 00:43:27 -07:00
David Harris
e764d4322c fdiv cleanup 2022-09-19 00:32:34 -07:00
David Harris
cf0c20d489 Division working again for radix 2 with unified OTFC 2022-09-19 00:30:30 -07:00
David Harris
b636072914 Unified on-the-fly conversion working for radix 2; broke radix-4 division 2022-09-19 00:04:00 -07:00
David Harris
4dbe1035cb Added 2 bits to C to initialize properly 2022-09-18 22:44:22 -07:00
David Harris
f202eb0f6f Added 2 bits to C to initialize properly 2022-09-18 22:42:35 -07:00
David Harris
cff3c2535d Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-09-18 21:27:36 -07:00
David Harris
498c053aab FP testbench 2022-09-18 21:27:21 -07:00
David Harris
f38bb5b32e Divide testfloat starts with half-precision tests 2022-09-18 06:46:47 -07:00
Ross Thompson
57c366c1b2 Removed NonIROM and NonDTIM select signals from IFU and LSU. 2022-09-17 22:01:03 -05:00
Ross Thompson
cb34b7c98f Found the ahb burst bug. 
We had instruction fetches fixed HSIZE = 2 (4 bytes) for all requests.  It should be HSIZE = 3 (8 bytes) for cache fetches and 4 for uncached reads.  The reason this worked for non burst is the DDR4 memory controller returns the full double word even for 4 byte reads.  In burst mode the second beat ending up pointing to the next 4 bytes rather than the next 8 bytes.
 2022-09-17 20:30:01 -05:00
David Harris
b74a68ff0f Reduced number of cycles required for lower-precision sqrt 2022-09-17 09:55:34 -07:00
David Harris
ac78823f6c Starting to adust number of cycles for division/sqrt 2022-09-17 05:58:59 -07:00
cturek
79addec27a Fixed j1 to align with new C reg 2022-09-16 02:15:48 +00:00
Kip Macsai-Goren
cc7d1c8ef9 Created initial endianness tests 2022-09-16 01:06:26 +00:00
David Harris
8f2b3b2387 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-09-15 12:49:21 -07:00
David Harris
94dca9194e renamed endianswap 2022-09-15 12:49:18 -07:00
Ross Thompson
38e114a6c0 Fixed subword read to work with bigendian. 2022-09-15 14:08:04 -05:00
David Harris
29d9ded25c FDIVSQRT cleanup 2022-09-15 09:10:57 -07:00
Ross Thompson
cea012a640 renamed multimanager to multicontroller. 2022-09-14 14:03:37 -05:00
Ross Thompson
bf6468a24c Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-09-14 13:59:22 -05:00
cturek
da67e02392 Added shift for radix 4 sqrt 2022-09-14 17:34:24 +00:00
cturek
47d02db2eb Moved X-1 to preproc 2022-09-14 17:26:56 +00:00
cturek
fe77b5e37b Delete srt 2022-09-14 17:02:42 +00:00
cturek
4f3baea0fc removed unnecessary XZero from wsmux 2022-09-14 16:59:52 +00:00
David Harris
14bbd07e63 ZMerge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-09-14 09:42:17 -07:00
Ross Thompson
2c86badeb2 pipelining of fetch into evict AHB requests. 2022-09-13 17:51:55 -05:00
Ross Thompson
c7d3580637 Renamed signals in the LSU. 2022-09-13 11:47:39 -05:00
David Harris
1495305045 Removed unused signals 2022-09-12 11:35:35 -07:00
David Harris
7197a6de44 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-09-08 16:05:58 -07:00
David Harris
7639c05e51 Moved C to shift before rather than after using in an iteration 2022-09-08 16:05:53 -07:00
David Harris
7ba9b0b349 divsqrt comment cleanup 2022-09-08 15:40:42 -07:00
Ross Thompson
c4a7d3c147 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-09-08 17:15:46 -05:00
David Harris
5ea82cff33 CSA-based completion detection 2022-09-08 14:58:08 -07:00
Ross Thompson
7f1ae039b0 Optimization. Able to remove hptw address muxes from the E stage. 2022-09-08 15:51:18 -05:00
Ross Thompson
0904951a8c Oups the ahbinterface.sv was accidentally named abhinterface.sv. 2022-09-08 13:21:37 -05:00
Ross Thompson
6e8d97e921 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-09-07 16:36:51 -05:00
Ross Thompson
f4e3036593 Oups fixed order of ending swap with mux between cache and fetch buffer. 2022-09-07 16:29:47 -05:00
David Harris
2d5e7827df Factored out aplusbeq0 unit 2022-09-07 11:36:35 -07:00
David Harris
c730ddf74a Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-09-07 11:11:39 -07:00
David Harris
7a29f9c95b Running 16-bit square root cases first in testfloat 2022-09-07 11:11:35 -07:00
Ross Thompson
0615798467 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-09-07 12:26:50 -05:00
David Harris
ce6e153b15 Run 16-bit fsqrt tests first 2022-09-07 10:26:09 -07:00
Ross Thompson
83306ec238 Named change for ahb tests to be less annoying. 2022-09-07 12:24:41 -05:00
David Harris
838d98cf4b Preprocessing cleanup 2022-09-07 10:21:27 -07:00
Ross Thompson
3571fb18c2 Modified regression tests to add some ahb configurations. 2022-09-07 12:03:58 -05:00
David Harris
dff9416a33 Added rv32i config for regression of wally32periph 2022-09-07 09:37:59 -07:00
Ross Thompson
5a0cda9860 Merge branch 'multimanager' into main 2022-09-07 10:54:27 -05:00
David Harris
c8e0ea067e Continued simplifying fdivsqrt postprocessing 2022-09-07 07:02:22 -07:00
David Harris
b0ff3a0952 Continued simplifying fdivsqrt postprocessing 2022-09-07 07:00:13 -07:00
David Harris
9e7926e8d7 Moving postprocessing into postproc block 2022-09-07 06:42:37 -07:00
David Harris
c39e71f168 fdivsqrtfsm cleanup 2022-09-07 06:32:07 -07:00
David Harris
027b303b20 fdivsqrtfsm cleanup 2022-09-07 06:27:01 -07:00
David Harris
19e449b83d Fixed regression for divsqrt radix2 2022-09-07 06:12:23 -07:00
Ross Thompson
7ad7cea25b James found a bug in synchronizer. Was not actually back to back flip flops. 2022-09-06 15:06:54 -05:00
Ross Thompson
bc15f6c5e4 Added logic to make burst optional. 2022-09-06 09:21:21 -05:00
Ross Thompson
68a200d728 Added generate around the longer latency version of the ram_ahb.sv 2022-09-06 09:21:03 -05:00
Ross Thompson
20643ffc4a Names changes. 2022-09-05 20:49:35 -05:00
Ross Thompson
2554f96662 Cleaned up hacks to ram. 2022-09-04 14:52:40 -05:00
Ross Thompson
c87268baf1 Modified ram_ahb to work with different latencies. 2022-09-04 14:46:15 -05:00
Ross Thompson
f9daa7f6b9 Progress towards fixing the select HREADY muxing in uncore. 2022-09-04 13:07:49 -05:00
Ross Thompson
221367efb9 Disabled AHB burst mode, which discovered a bug. 
Multimanger bug in how back to back requests were arbitrated.
 2022-09-03 22:31:41 -05:00
cturek
254bb8e0a0 Old changes to old files 2022-09-03 22:09:55 +00:00
Ross Thompson
d601fdf186 Possible fix to AHB burst eviction bug. If HREADY went low during a burst seq the next data phase would only last 1 cycle. 2022-09-02 19:58:41 -05:00
Ross Thompson
00cffb0aa5 Renamed state in buscachefsm to match AHB phases. 2022-09-02 17:17:40 -05:00
Ross Thompson
6f2acf678c Renamed states in busfsm to match AHB phases and book names. 2022-09-02 17:12:36 -05:00
Ross Thompson
6f366c643d Possible fix for AHB trailing ~HREADY bug. 2022-09-02 16:58:35 -05:00
Ross Thompson
3361a06c62 Merge branch 'multimanager' of github.com:davidharrishmc/riscv-wally into multimanager 2022-09-02 16:31:07 -05:00
Ross Thompson
5d2b299182 Fixed brom1p1r.sv to have fpga preload. 2022-09-02 15:49:50 -05:00
Ross Thompson
c1de88d929 Merge branch 'multimanager' of github.com:davidharrishmc/riscv-wally into multimanager 2022-09-02 13:54:48 -05:00
Ross Thompson
4d60d9a840 Fixed up FPGA constraints. 
Added back in the fpga boot rom preload.
 2022-09-02 13:54:35 -05:00
David Harris
41448663b9 Initial radix 4 square root debuggin 2022-09-01 16:57:57 -07:00
Ross Thompson
055b55402f clean up subword write. 2022-09-01 17:55:19 -05:00
David Harris
5e26bcced1 Fixed lint errors in square root and improved waveforms in testfloat 2022-09-01 15:49:13 -07:00
Ross Thompson
eae56a890c marked possible improvement to ahb bus fsms. 2022-08-31 23:57:08 -05:00
David Harris
199296dd03 fdiv debug 2022-08-31 14:26:31 -07:00
Ross Thompson
7598fbcb3b Reduced busfsm to 3 states! 2022-08-31 16:11:59 -05:00
Ross Thompson
6f3dad8207 Simplified. 2022-08-31 15:40:56 -05:00
Ross Thompson
0f2315e8a1 more renaming. 2022-08-31 14:52:06 -05:00
Ross Thompson
12d1ef2144 More renaming. 2022-08-31 14:49:08 -05:00
Ross Thompson
c03b202ab0 Moved files. 
Encapsulated ahbinterface.
 2022-08-31 14:45:01 -05:00
Ross Thompson
f2f1169a04 Renamed AHBCachebusdp to abhcacheinterface. 2022-08-31 14:12:19 -05:00
Ross Thompson
1b339f0547 Moved files around. 2022-08-31 14:08:06 -05:00
Ross Thompson
cc7b35b831 Merge branch 'multimanager' into main 2022-08-31 13:10:22 -05:00
Ross Thompson
10817f7885 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-08-31 13:10:04 -05:00
David Harris
09456db445 Checking in radix 4 square root with qsel, fgen, softc, but not working 2022-08-31 10:54:50 -07:00
Ross Thompson
0d3f03ac06 Major cleanup of multimanager. 2022-08-31 12:40:25 -05:00
Ross Thompson
77cc549cfa Cleanup multimanager. 2022-08-31 12:04:44 -05:00
Ross Thompson
f3d611c686 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-08-31 11:38:29 -05:00
Ross Thompson
eaa9cbda46 cleanup of multimanager. 2022-08-31 11:38:06 -05:00
Ross Thompson
a0f681944c More Cleanup. 2022-08-31 11:21:02 -05:00
Ross Thompson
8156109add More cleanup. 2022-08-31 11:12:38 -05:00
Ross Thompson
4b167ad21e More simplifications. 2022-08-31 10:45:16 -05:00
Ross Thompson
a93c5b0f0a Trade off. Added additional state to bus fsm separating STATE_CACHE_ACCESS into STATE_CACHE_FETCH and STATE_CACHE_EVICT. This allows removing CacheRWDelay. Saves a bit of logic but fsm is more complex. Also the fsm outputs are simplier. 2022-08-31 10:36:30 -05:00
Ross Thompson
ed2a9225ea Removed unused old versions of the bus controllers. 2022-08-31 09:51:54 -05:00
Ross Thompson
89f13370e2 Removed old signals. 2022-08-31 09:50:39 -05:00
DTowersM
48a1abf06f Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally 2022-08-31 00:18:04 +00:00
DTowersM
bdeb5c6509 fixed qrduino keyerror in embench test 2022-08-31 00:17:58 +00:00
Ross Thompson
5409501ca6 Maybe fixed it? 2022-08-30 18:08:34 -05:00
Ross Thompson
cce3fdd0e3 Updates to wave file. 2022-08-30 17:34:36 -05:00
Ross Thompson
8b9f30c91a more progress. 2022-08-30 17:32:32 -05:00
Ross Thompson
fab3a2b791 Temporary commit. 2022-08-30 15:40:42 -05:00
Ross Thompson
315f662eb9 More progress. 2022-08-30 15:27:19 -05:00
Ross Thompson
637d60b64c Progress. 2022-08-30 14:17:00 -05:00
David Harris
e1760dde55 Fixed checking termination in testfloat testbench 2022-08-30 10:55:21 -07:00
Ross Thompson
8cf3c7b352 new cache bus fsm not working but lints. 
Forgot a few files in the last commit.
 2022-08-30 10:58:07 -05:00
Ross Thompson
a2220fc142 Have a rough working multi manager! 2022-08-29 17:11:27 -05:00
Ross Thompson
f5584bb41c Modified rv32e configuration to use a true ahb bus interface in the lsu and ifu. 2022-08-29 17:04:53 -05:00
David Harris
28db4fdc70 commented out lines to have divider work again 2022-08-29 13:01:32 -07:00
David Harris
87b77658f2 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-08-29 12:01:13 -07:00
David Harris
a6efbb3fda Initial FDIVSQRT simplification working 2022-08-29 12:01:09 -07:00
Ross Thompson
233777f744 Part way through the updated bus fsm for direct AHB in lsu/ifu + multi-manager. 2022-08-29 13:01:24 -05:00
Ross Thompson
e805f33f4e Typo. 2022-08-29 11:40:35 -05:00
Ross Thompson
dceaf6e4e3 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-08-29 11:38:37 -05:00
Ross Thompson
e7de0e033e Added comments about planned changes. 2022-08-29 09:48:00 -05:00
David Harris
a82cf3d0ba Simplify FSM 2022-08-29 04:32:27 -07:00
David Harris
7856f08e1d Renamed special case 2022-08-29 04:29:58 -07:00
David Harris
7d4e85bf21 Separated out radix 2 and radix 4 stages into different modules 2022-08-29 04:26:14 -07:00
David Harris
2788022c22 renamed srt to fdivsqrt 2022-08-29 04:04:05 -07:00
Ross Thompson
7b76fbaa9a Removed ignore request from busfsm. 2022-08-28 21:12:27 -05:00
Ross Thompson
122c88ee46 Created two new pma regions for dtim and irom. 2022-08-28 13:50:50 -05:00
Ross Thompson
5e63af5887 Reordered the adrdecs. 2022-08-28 13:38:57 -05:00
Ross Thompson
dd7736cb93 Possible fix. 2022-08-28 13:10:47 -05:00
Ross Thompson
a81fcc6b4b Partial fix to bus + dtim. 2022-08-27 23:44:17 -05:00
David Harris
f2517f8290 Preliminary work to make DTIM and Bus compatible. Not yet working because accesses to bus are causing illegal address faults on the bus. 2022-08-27 20:31:09 -07:00
David Harris
60b673cafd Adding decoding for dtim. Added rv32ic_wally32periph test, which should hang until decoder overrides bus 2022-08-27 05:31:56 -07:00
David Harris
4aa30c48aa fixed wally-config 2022-08-26 22:13:10 -07:00
David Harris
37f0b52520 Fixed address decoder hanging buildroot 2022-08-26 22:01:25 -07:00
David Harris
d0dbc74492 Fixed DTIM/IROM_BASE number of bits in buildroot/fpga configs 2022-08-26 21:29:26 -07:00
David Harris
2b241f8bbd Set bit width of DMEM/IROM_SUPPORTED and fixed address decoding 2022-08-26 21:18:18 -07:00
David Harris
03e731b3ff Set correct size of IROM/DTIM and allow FLEN>XLEN with DTIM 2022-08-26 21:05:20 -07:00
David Harris
f0b4f69b65 Added IROM and DTIM decoding to adrdecs 2022-08-26 20:45:43 -07:00
David Harris
812158aeee Replaced DTIM and IROM with DTIM_SUPPORTED, IROM_SUPPORTED, and base and range for each 2022-08-26 20:26:12 -07:00
David Harris
95dd50a567 Renamed DMEM to DTIM and added checks about compatibility of DTIM/IROM and virtmem 2022-08-26 20:12:03 -07:00
David Harris
ca6837f597 Fixed endian swapping on bus only 2022-08-26 19:58:04 -07:00
David Harris
5f37e16b62 Fixed rv32e LSU and IFU issues 2022-08-25 20:02:38 -07:00
David Harris
671ea60f3e lsu simplification 2022-08-25 18:52:42 -07:00
David Harris
ec2c6d4fcb busfsm simplified 2022-08-25 18:36:53 -07:00
David Harris
f262abb5c3 Removed unused signals 2022-08-25 18:34:39 -07:00
David Harris
b73286ece6 Removed unused signals 2022-08-25 18:30:46 -07:00
David Harris
949e76bc83 Removed UncachedBusRead and UncachedBusWrite 2022-08-25 18:24:39 -07:00
David Harris
e39694694c Restored ahbtranstype 2022-08-25 18:22:26 -07:00
David Harris
83d3782f2c Removed ahbtranstype 2022-08-25 18:21:45 -07:00
David Harris
543fbd1fa9 Removed WordCountFlag 2022-08-25 18:21:18 -07:00
David Harris
d118fcbde8 Removed UncachedAccess 2022-08-25 18:20:52 -07:00
David Harris
bac95823b6 Removed UncachedRW 2022-08-25 18:19:41 -07:00
David Harris
cfcde754c3 Removed CacheBusAck 2022-08-25 18:17:34 -07:00
David Harris
9bc62ce124 Removed SelUncachedAdr 2022-08-25 18:15:59 -07:00
David Harris
f39e62eeea Removed Cache_Enabled 2022-08-25 18:13:34 -07:00
David Harris
5bfaf31df0 Removed STATE_BUS_FETCH and STATE_BUS_WRITE 2022-08-25 18:12:09 -07:00
David Harris
85e93e2bb7 Removed CacheFetchLine and CacheWriteLine 2022-08-25 18:10:15 -07:00
David Harris
23a102b1b9 Removed CountEn 2022-08-25 18:05:44 -07:00
David Harris
e485e986a5 Removed wordcount 2022-08-25 18:04:49 -07:00
David Harris
69dff87feb Added buscachefsm for system with bus and cache 2022-08-25 18:01:01 -07:00
David Harris
5340c45dfc Separated busdp for cache from simpler logic for no cache 2022-08-25 17:54:04 -07:00
David Harris
9a92bfe095 Simplified swbytemask 2022-08-25 17:32:16 -07:00
David Harris
eb753b3b3f FIxed wallypipelinedsoc merge conflict 2022-08-25 15:36:47 -07:00
David Harris
902d2067ba Removed delayed AHB signals from top level 2022-08-25 15:34:14 -07:00
Ross Thompson
db635e3ad2 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-08-25 16:01:02 -05:00
Ross Thompson
8c8b95ecf5 Finally resolved the issues with the rv32ic and rv64ic configurations. 2022-08-25 16:00:55 -05:00
Ross Thompson
5c2bc20dbd Almost fixed issues with irom and dtim address selection. 2022-08-25 15:52:25 -05:00
David Harris
302a7fa294 Extended HADDR to PA_BITS 2022-08-25 13:11:36 -07:00
Ross Thompson
179aec3616 Still not working with rv32ic. 2022-08-25 15:03:54 -05:00
David Harris
07225cabb7 Fixed brom name 2022-08-25 12:48:00 -07:00
Ross Thompson
d23888407b Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-08-25 14:45:02 -05:00
David Harris
1226b2889e ahblite cleanup 2022-08-25 12:44:25 -07:00
Ross Thompson
3b612d6201 Possible fixes for earily messup of rv32ic and rv64ic configs. 2022-08-25 14:42:08 -05:00
Ross Thompson
f67010c688 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-08-25 14:40:52 -05:00
David Harris
bc0c7d0cd8 Cleaned up SelBusWord 2022-08-25 11:18:13 -07:00
David Harris
c442dea173 Removed M sufix from busdp signals 2022-08-25 11:13:01 -07:00
David Harris
48f346baf8 Renamed LSUFunct3M to Funct3 in busdp 2022-08-25 11:08:12 -07:00
David Harris
9bada9c14a Renaming LSU signals from busdp 2022-08-25 11:05:10 -07:00
David Harris
3ba961d1a8 renamed BusBuffer to FetchBuffer 2022-08-25 10:44:39 -07:00
David Harris
dda3b441d7 Continued busdp/ebu simplification 2022-08-25 10:20:02 -07:00
David Harris
19fe6d106c Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-08-25 09:52:49 -07:00
David Harris
aba914ea5e Renamed AHB signals coming out of LSU to LSH_<AHBNAME> 2022-08-25 09:52:08 -07:00
Ross Thompson
e605ef57dc BROKEN. Don't use this commit. 
Issue running cacheless with bus.
 2022-08-25 11:02:46 -05:00
Ross Thompson
b0aea77b20 Added generate around uncore. 2022-08-25 10:35:24 -05:00
Ross Thompson
01a7718471 Added generate around ebu. 2022-08-25 09:24:13 -05:00
Ross Thompson
ad485fe591 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-08-25 09:03:34 -05:00
Ross Thompson
701324eeb8 Updated ila signals. 
Improve fpga wave config.
added back in the fpga preload.
 2022-08-25 09:03:29 -05:00
David Harris
ae0702d129 Renamed DCache to Cache in busdp/busfsm signal interface 2022-08-25 06:21:22 -07:00
David Harris
3500286803 Cleanup typos 2022-08-25 04:32:19 -07:00
David Harris
db5c941d6f Minor name cleanups 2022-08-25 04:28:25 -07:00
David Harris
1206b388c7 Replaced dtim with rom-based IROM in IFU. Moved cache control signals out of DTIM and IROM 2022-08-25 04:06:27 -07:00
David Harris
f7209627c2 removed simpleram and modified dtim to use bram1p1rw 2022-08-25 03:39:57 -07:00
David Harris
562be633ab Stripped write capaibilty out of rom_ahb 2022-08-24 17:23:08 -07:00
David Harris
a131e1f17a Added ROM module and moved memories into generic/mem 2022-08-24 17:03:22 -07:00
David Harris
6785644fb8 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-08-24 16:30:28 -07:00
David Harris
b21b91234b Ram cleanup 2022-08-24 16:30:25 -07:00
Ross Thompson
d10edfa5e0 No longer need wally-pipelined-fpga.do. 2022-08-24 18:10:45 -05:00
Ross Thompson
769af32f2a Renamed RAM to UNCORE_RAM. 2022-08-24 18:09:07 -05:00
Ross Thompson
fc22e807e2 Merged testbench-fpga into testbench. 
Modified SDC to simplify LimitTimers.  LimitTimers needs to be 0 for implmementation and 1 for simulation.
 2022-08-24 17:52:25 -05:00
Ross Thompson
4a371b6829 added SD card and external ram to common testbench. 2022-08-24 13:27:18 -05:00
Ross Thompson
d23b309e0d Fixed lint errors with bram wrapper. 2022-08-24 13:19:23 -05:00
Ross Thompson
51adf6cba9 Modified the lsu/ifu memory configurations. 2022-08-24 12:35:15 -05:00
David Harris
bcb52acfba bram synthesis test 2022-08-23 19:34:45 -07:00
Ross Thompson
e4cbb43c67 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-08-23 18:52:15 -05:00
Ross Thompson
642dc170d7 Found small bug in busfsm which was issuing 1 extra memory read after each cache line fetch. Does not appear to have translated to an extra read out of ahblite. 2022-08-23 18:51:11 -05:00
David Harris
5eebd521c5 Fixed FPU-IEU forwarding stall 2022-08-23 14:14:41 -07:00
David Harris
d72068d582 Only stall FPU to IEU on convert instructions with dependencies 2022-08-23 12:57:18 -07:00
David Harris
05aa18fe14 Cleaned up fcvt selection control to IEU and FPUIllegalInst signals 2022-08-23 12:17:19 -07:00
David Harris
d19fc99bf0 Simplify IEU-FP datapath 2022-08-23 11:16:36 -07:00
David Harris
f72d07adce Improved illegal instruction checking in FPU 2022-08-23 11:08:02 -07:00
David Harris
c61dba6192 Fixed LSU typos 2022-08-23 10:23:08 -07:00
David Harris
2a1bd53663 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-08-23 10:14:59 -07:00
David Harris
029aecabf7 typo in srtfsm 2022-08-23 10:14:54 -07:00
Katherine Parry
fe0c6afe58 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally 2022-08-23 16:36:32 +00:00
Katherine Parry
4e33ead413 renamed rounding bits to L,G,R,S and fixed lint warning 2022-08-23 16:36:20 +00:00
Ross Thompson
8d4301e2f6 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-08-23 11:15:04 -05:00
Ross Thompson
20ba6fd19c Reversed order of supported sized in adrdecs. 2022-08-23 11:14:53 -05:00
Ross Thompson
5efec3b1f3 Replaced FPU data replicaiton on WriteData bus with 0 extention. 2022-08-23 10:46:03 -05:00
Ross Thompson
aa5cbab0d8 Replaced LSU data replication with 0 extention. 2022-08-23 10:43:47 -05:00
Ross Thompson
3b07584403 Updated the names of the *WriteDataM inside the LSU to more meaningful names. 
Moved the FWriteDataMux so that the bus and dtim both get fpu stores.
Modified the PMA to disallow double sized reads when XLEN=32.
 2022-08-23 10:34:39 -05:00
David Harris
7fcc852687 Q depends on D 2022-08-23 08:29:59 -07:00
David Harris
e714b75888 LSU minor edits 2022-08-23 07:35:47 -07:00
David Harris
16a92eaf10 Updated testbench assertions. 2022-08-23 07:23:24 -07:00
David Harris
3c91df95d9 Named HTRANS states in busfsm 2022-08-22 13:56:46 -07:00
David Harris
6cfbf95d98 Renamed signals for LSU - FPU interface 2022-08-22 13:47:56 -07:00
David Harris
c789b5789c renamed GrantData to LSUGrant 2022-08-22 13:47:19 -07:00
David Harris
0e489443f2 Finished FPU-LSU interface cleanup 2022-08-22 13:43:04 -07:00
David Harris
ea153e0aad Removed FStore2 and simplified HPTW 2022-08-22 13:29:54 -07:00
David Harris
8444eca57c Simplified FPU-LSU interface to skip IEU 2022-08-22 13:29:20 -07:00
David Harris
774cddf33c Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-08-22 13:28:54 -07:00
David Harris
d556adde16 Simplified FPU-LSU interface to skip IEU 2022-08-22 13:28:51 -07:00