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lsu simplification

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This commit is contained in:
David Harris 2022-08-25 18:52:42 -07:00
parent ec2c6d4fcb
commit 671ea60f3e
2 changed files with 11 additions and 13 deletions
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3
pipelined/src/lsu/dtim.sv
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@ -36,7 +36,6 @@ module dtim(
input logic TrapM,
input logic [`LLEN-1:0] WriteDataM,
input logic [`LLEN/8-1:0] ByteMaskM,
input logic Cacheable,
output logic [`LLEN-1:0] ReadDataWordM
);
@ -46,7 +45,7 @@ module dtim(
localparam ADDR_WDITH = $clog2(`UNCORE_RAM_RANGE/8); // *** this is the wrong size
localparam OFFSET = $clog2(`LLEN/8);
assign we = LSURWM[0] & Cacheable & ~TrapM; // have to ignore write if Trap.
assign we = LSURWM[0] & ~TrapM; // have to ignore write if Trap.
bram1p1rw #(`LLEN/8, 8, ADDR_WDITH)
ram(.clk, .we, .bwe(ByteMaskM), .addr(IEUAdrE[ADDR_WDITH+OFFSET-1:OFFSET]), .dout(ReadDataWordM), .din(WriteDataM));

21
pipelined/src/lsu/lsu.sv
View File

@ -202,14 +202,11 @@ module lsu (
dtim dtim(.clk, .reset, .LSURWM,
.IEUAdrE(CPUBusy | LSURWM[0] | reset ? IEUAdrM : IEUAdrE),
.TrapM, .WriteDataM(LSUWriteDataM),
.ReadDataWordM(ReadDataWordM[`XLEN-1:0]), .ByteMaskM(ByteMaskM[`XLEN/8-1:0]), .Cacheable(CacheableM));
.ReadDataWordM(ReadDataWordM[`XLEN-1:0]), .ByteMaskM(ByteMaskM[`XLEN/8-1:0]));
// since we have a local memory the bus connections are all disabled.
// There are no peripherals supported.
// *** this will have to change to support TIM and bus (DH 8/25/22)
assign {BusStall, LSUBusWrite, LSUBusRead, BusCommittedM} = '0;
assign {DCacheStallM, DCacheCommittedM} = '0;
assign {DCacheMiss, DCacheAccess} = '0;
end
if (`BUS) begin : bus
localparam integer WORDSPERLINE = `DCACHE ? `DCACHE_LINELENINBITS/`XLEN : 1;
@ -256,20 +253,22 @@ module lsu (
busfsm #(LOGBWPL) busfsm(
.clk, .reset, .IgnoreRequest, .RW(LSURWM),
.BusAck(LSUBusAck), .BusInit(LSUBusInit), .CPUBusy, .BusStall, .BusWrite(LSUBusWrite),
.BusRead(LSUBusRead),
.HTRANS(LSUHTRANS),
.BusCommitted(BusCommittedM));
.BusAck(LSUBusAck), .BusInit(LSUBusInit), .CPUBusy,
.BusStall, .BusWrite(LSUBusWrite), .BusRead(LSUBusRead),
.HTRANS(LSUHTRANS), .BusCommitted(BusCommittedM));
// *** possible bug - ReadDatWordM vs. ReadDataWordMuxW - is byte swapping needed for endian
assign LSUHBURST = 3'b0;
assign LSUTransComplete = BusAck;
assign LSUTransComplete = LSUBusAck;
assign {ReadDataWordM, DCacheStallM, DCacheCommittedM, DCacheFetchLine, DCacheWriteLine} = '0;
assign DCacheMiss = CacheableM; assign DCacheAccess = CacheableM;
end
assign {DCacheMiss, DCacheAccess} = '0;
end
end else begin: nobus // block: bus
assign LSUHWDATA = '0;
assign ReadDataWordMuxM = LittleEndianReadDataWordM;
assign {BusStall, BusCommittedM} = '0;
assign {DCacheMiss, DCacheAccess} = '0;
assign {DCacheStallM, DCacheCommittedM} = '0;
end
/////////////////////////////////////////////////////////////////////////////////////////////