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https://github.com/openhwgroup/cvw
synced 2025-02-11 06:05:49 +00:00
Removed old signals.
This commit is contained in:
Ross Thompson
parent
5409501ca6
commit
89f13370e2
8
pipelined/src/cache/AHBBuscachefsm.sv
vendored
8
pipelined/src/cache/AHBBuscachefsm.sv
vendored
@ -74,15 +74,14 @@ module AHBBuscachefsm #(parameter integer WordCountThreshold,
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logic [LOGWPL-1:0] NextWordCount;
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logic WordCountFlag;
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logic [2:0] LocalBurstType;
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logic CntReset;
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logic WordCntReset;
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logic [1:0] RWDelay, CacheRWDelay;
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assign CntReset = BusNextState == STATE_READY;
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// Used to send address for address stage of AHB.
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flopenr #(LOGWPL)
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WordCountReg(.clk(HCLK),
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.reset(~HRESETn | CntReset),
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.reset(~HRESETn | WordCntReset),
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.en(WordCntEn),
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.d(NextWordCount),
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.q(WordCount));
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@ -90,7 +89,7 @@ module AHBBuscachefsm #(parameter integer WordCountThreshold,
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// Used to store data from data phase of AHB.
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flopenr #(LOGWPL)
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WordCountDelayedReg(.clk(HCLK),
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.reset(~HRESETn | CntReset),
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.reset(~HRESETn | WordCntReset),
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.en(WordCntEn),
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.d(WordCount),
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.q(WordCountDelayed));
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@ -99,6 +98,7 @@ module AHBBuscachefsm #(parameter integer WordCountThreshold,
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assign WordCountFlag = (WordCountDelayed == WordCountThreshold[LOGWPL-1:0] ); // Detect when we are waiting on the final access.
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assign WordCntEn = (BusNextState == STATE_CACHE_ACCESS & HREADY) |
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(BusNextState == STATE_READY & |CacheRW & HREADY);
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assign WordCntReset = BusNextState == STATE_READY;
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// replace with fsm with two more states.
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flopenr #(2) RWReg(HCLK, ~HRESETn, 1'b1, RW, RWDelay);
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@ -37,16 +37,12 @@ module ifu (
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input logic FlushF, FlushD, FlushE, FlushM,
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// Bus interface
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(* mark_debug = "true" *) input logic [`XLEN-1:0] HRDATA,
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(* mark_debug = "true" *) input logic IFUBusAck,
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(* mark_debug = "true" *) input logic IFUBusInit,
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(* mark_debug = "true" *) output logic [`PA_BITS-1:0] IFUHADDR,
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(* mark_debug = "true" *) output logic IFUBusRead,
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(* mark_debug = "true" *) output logic IFUStallF,
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(* mark_debug = "true" *) output logic [2:0] IFUHBURST,
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(* mark_debug = "true" *) output logic [1:0] IFUHTRANS,
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(* mark_debug = "true" *) output logic IFUHWRITE,
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(* mark_debug = "true" *) input logic IFUHREADY,
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(* mark_debug = "true" *) output logic IFUTransComplete,
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(* mark_debug = "true" *) output logic [`XLEN-1:0] PCF,
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// Execute
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output logic [`XLEN-1:0] PCLinkE,
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@ -250,24 +246,16 @@ module ifu (
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flopen #(`XLEN) fb(.clk, .en(CaptureEn), .d(HRDATA), .q(AllInstrRawF[31:0]));
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/* -----\/----- EXCLUDED -----\/-----
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busfsm #(LOGBWPL) busfsm(
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.clk, .reset, .RW(NonIROMMemRWM & ~{ITLBMissF, ITLBMissF}),
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.BusAck(IFUBusAck), .BusInit(IFUBusInit), .CPUBusy,
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.BusStall, .BusWrite(), .BusRead(IFUBusRead),
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.HTRANS(IFUHTRANS), .BusCommitted());
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-----/\----- EXCLUDED -----/\----- */
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AHBBusfsm busfsm(.HCLK(clk), .HRESETn(~reset), .RW(NonIROMMemRWM & ~{ITLBMissF, ITLBMissF}), .CaptureEn,
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.BusCommitted(), .CPUBusy, .HREADY(IFUHREADY), .BusStall, .HTRANS(IFUHTRANS), .HWRITE(IFUHWRITE));
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assign IFUHBURST = 3'b0;
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assign IFUTransComplete = IFUBusAck;
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assign {ICacheFetchLine, ICacheStallF, FinalInstrRawF} = '0;
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assign {ICacheMiss, ICacheAccess} = '0;
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end
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end else begin : nobus // block: bus
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assign {BusStall, IFUBusRead} = '0;
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assign BusStall = '0;
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assign {ICacheStallF, ICacheMiss, ICacheAccess} = '0;
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assign AllInstrRawF = FinalInstrRawF;
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end
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@ -72,10 +72,6 @@ module lsu (
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output logic StoreAmoMisalignedFaultM, StoreAmoAccessFaultM,
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// connect to ahb
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(* mark_debug = "true" *) output logic [`PA_BITS-1:0] LSUHADDR,
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(* mark_debug = "true" *) output logic LSUBusRead,
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(* mark_debug = "true" *) output logic LSUBusWrite,
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(* mark_debug = "true" *) input logic LSUBusAck,
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(* mark_debug = "true" *) input logic LSUBusInit,
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(* mark_debug = "true" *) input logic [`XLEN-1:0] HRDATA,
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(* mark_debug = "true" *) output logic [`XLEN-1:0] LSUHWDATA,
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(* mark_debug = "true" *) input logic LSUHREADY,
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@ -84,7 +80,6 @@ module lsu (
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(* mark_debug = "true" *) output logic [2:0] LSUHBURST,
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(* mark_debug = "true" *) output logic [1:0] LSUHTRANS,
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(* mark_debug = "true" *) output logic [`XLEN/8-1:0] LSUHWSTRB,
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(* mark_debug = "true" *) output logic LSUTransComplete,
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// page table walker
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input logic [`XLEN-1:0] SATP_REGW, // from csr
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input logic STATUS_MXR, STATUS_SUM, STATUS_MPRV,
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@ -278,6 +273,7 @@ module lsu (
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flop #(`XLEN) wdreg(clk, LSUHWDATA_noDELAY, LSUHWDATA); // delay HWDATA by 1 cycle per spec; *** assumes AHBW = XLEN
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// *** bummer need a second byte mask for bus as it is XLEN rather than LLEN.
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// probably can merge by muxing LSUPAdrM's LLEN/8-1 index bit based on HTRANS being != 0.
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logic [`XLEN/8-1:0] BusByteMaskM;
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swbytemask #(`XLEN) busswbytemask(.Size(LSUHSIZE), .Adr(LSUPAdrM[$clog2(`XLEN/8)-1:0]), .ByteMask(BusByteMaskM));
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@ -294,21 +290,12 @@ module lsu (
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flop #(`XLEN) wdreg(clk, LSUWriteDataM, LSUHWDATA); // delay HWDATA by 1 cycle per spec; *** assumes AHBW = XLEN
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flop #(`XLEN/8) HWSTRBReg(clk, ByteMaskM, LSUHWSTRB);
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/* -----\/----- EXCLUDED -----\/-----
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busfsm #(LOGBWPL) busfsm(
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.clk, .reset, .RW(LSURWM & ~{IgnoreRequest, IgnoreRequest}),
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.BusAck(LSUBusAck), .BusInit(LSUBusInit), .CPUBusy,
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.BusStall, .BusWrite(LSUBusWrite), .BusRead(LSUBusRead),
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.HTRANS(LSUHTRANS), .BusCommitted(BusCommittedM));
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-----/\----- EXCLUDED -----/\----- */
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AHBBusfsm busfsm(.HCLK(clk), .HRESETn(~reset), .RW(LSURWM & ~{IgnoreRequest, IgnoreRequest}),
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.BusCommitted(BusCommittedM), .CPUBusy, .BusStall, .CaptureEn, .HREADY(LSUHREADY), .HTRANS(LSUHTRANS),
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.HWRITE(LSUHWRITE));
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assign ReadDataWordMuxM = LittleEndianReadDataWordM; // from byte swapping
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assign LSUHBURST = 3'b0;
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assign LSUTransComplete = LSUBusAck;
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assign {DCacheStallM, DCacheCommittedM, DCacheMiss, DCacheAccess} = '0;
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end
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end else begin: nobus // block: bus
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@ -133,19 +133,13 @@ module wallypipelinedcore (
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// AHB ifu interface
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logic [`PA_BITS-1:0] IFUHADDR;
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logic IFUBusRead;
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logic IFUBusAck, IFUBusInit;
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logic [2:0] IFUHBURST;
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logic [1:0] IFUHTRANS;
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logic IFUTransComplete;
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logic IFUHWRITE;
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logic IFUHREADY;
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// AHB LSU interface
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logic [`PA_BITS-1:0] LSUHADDR;
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logic LSUBusRead;
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logic LSUBusWrite;
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logic LSUBusAck, LSUBusInit;
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logic [`XLEN-1:0] LSUHWDATA;
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logic [`XLEN/8-1:0] LSUHWSTRB;
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logic LSUHWRITE;
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@ -161,7 +155,6 @@ module wallypipelinedcore (
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logic [2:0] LSUHSIZE;
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logic [2:0] LSUHBURST;
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logic [1:0] LSUHTRANS;
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logic LSUTransComplete;
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logic DCacheMiss;
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logic DCacheAccess;
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@ -178,8 +171,8 @@ module wallypipelinedcore (
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.StallF, .StallD, .StallE, .StallM,
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.FlushF, .FlushD, .FlushE, .FlushM,
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// Fetch
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.HRDATA, .IFUBusAck, .IFUBusInit, .PCF, .IFUHADDR,
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.IFUBusRead, .IFUStallF, .IFUHBURST, .IFUHTRANS, .IFUTransComplete,
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.HRDATA, .PCF, .IFUHADDR,
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.IFUStallF, .IFUHBURST, .IFUHTRANS,
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.IFUHREADY, .IFUHWRITE,
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.ICacheAccess, .ICacheMiss,
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@ -264,8 +257,8 @@ module wallypipelinedcore (
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.IEUAdrE, .IEUAdrM, .WriteDataM,
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.ReadDataW, .FlushDCacheM,
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// connected to ahb (all stay the same)
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.LSUHADDR, .LSUBusRead, .LSUBusWrite, .LSUBusAck, .LSUBusInit,
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.HRDATA, .LSUHWDATA, .LSUHWSTRB, .LSUHSIZE, .LSUHBURST, .LSUHTRANS, .LSUTransComplete,
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.LSUHADDR,
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.HRDATA, .LSUHWDATA, .LSUHWSTRB, .LSUHSIZE, .LSUHBURST, .LSUHTRANS,
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.LSUHWRITE, .LSUHREADY,
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// connect to csr or privilege and stay the same.
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@ -295,43 +288,14 @@ module wallypipelinedcore (
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// *** Ross: please make EBU conditional when only supporting internal memories
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if(`BUS) begin : ebu
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/* -----\/----- EXCLUDED -----\/-----
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ahblite ebu(// IFU connections
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.clk, .reset,
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.UnsignedLoadM(1'b0), .AtomicMaskedM(2'b00),
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.IFUHADDR, .IFUBusRead,
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.IFUHBURST,
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.IFUHTRANS,
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.IFUTransComplete,
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.IFUBusAck,
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.IFUBusInit,
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.IFUHWRITE,
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.IFUHREADY,
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// Signals from Data Cache
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.LSUHADDR, .LSUBusRead, .LSUBusWrite, .LSUHWDATA,
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.LSUHSIZE,
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.LSUHBURST,
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.LSUHTRANS,
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.LSUTransComplete,
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.LSUBusAck,
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.LSUBusInit,
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.LSUHWRITE,
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.LSUHREADY,
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.HREADY, .HRESP, .HCLK, .HRESETn,
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.HADDR, .HWDATA, .HWSTRB, .HWRITE, .HSIZE, .HBURST,
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.HPROT, .HTRANS, .HMASTLOCK);
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-----/\----- EXCLUDED -----/\----- */
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ahbmultimanager ebu(// IFU connections
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.clk, .reset,
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// IFU interface
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.IFUHADDR,
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.IFUHBURST,
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.IFUHTRANS,
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.IFUHREADY,
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// Signals from Data Cache
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// LSU interface
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.LSUHADDR,
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.LSUHWDATA,
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.LSUHWSTRB,
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@ -340,7 +304,7 @@ module wallypipelinedcore (
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.LSUHTRANS,
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.LSUHWRITE,
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.LSUHREADY,
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// BUS interface
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.HREADY, .HRESP, .HCLK, .HRESETn,
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.HADDR, .HWDATA, .HWSTRB, .HWRITE, .HSIZE, .HBURST,
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.HPROT, .HTRANS, .HMASTLOCK);
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