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Fixed checking termination in testfloat testbench

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This commit is contained in:
David Harris 2022-08-30 10:55:21 -07:00
parent 28db4fdc70
commit e1760dde55
4 changed files with 13 additions and 11 deletions
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2
pipelined/config/shared/wally-shared.vh
View File

@ -101,7 +101,7 @@
`define CORRSHIFTSZ ((`DIVRESLEN+`NF) > (3*`NF+8) ? (`DIVRESLEN+`NF) : (3*`NF+6))
// division constants
`define RADIX 32'h2
`define RADIX 32'h4
`define DIVCOPIES 32'h2
`define DIVLEN ((`NF < `XLEN) ? (`XLEN) : (`NF + 3))
// `define DIVN (`NF < `XLEN ? `XLEN : `NF+1) // length of input

2
pipelined/regression/testfloat.do
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@ -34,7 +34,7 @@ vlib work
# $num = the added words after the call
vlog +incdir+../config/$1 +incdir+../config/shared ../testbench/testbench-fp.sv ../src/fpu/*.sv ../src/generic/*.sv ../src/generic/flop/*.sv -suppress 2583,7063,8607,2697
vsim -voptargs=+acc work.testbenchfp -G TEST=$2
vsim -voptargs=+acc work.testbenchfp -G TEST=$2 -suppress 4014
view wave
#-- display input and output signals as hexidecimal values

8
pipelined/src/fpu/fdivsqrtfsm.sv
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@ -103,8 +103,8 @@ module fdivsqrtfsm(
end
flopr #(1) WZeroReg(clk, reset | DivStart, WZero, WZeroDelayed);
assign DivDone = (state == DONE);
// assign DivDone = (state == DONE) | (WZeroDelayed & (state == BUSY));
// assign DivDone = (state == DONE);
assign DivDone = (state == DONE) | (WZeroDelayed & (state == BUSY));
assign W = WC+WS;
assign NegSticky = W[`DIVb+3];
assign EarlyTermShiftE = step;
@ -123,8 +123,8 @@ module fdivsqrtfsm(
if (StallM) state <= #1 DONE;
else state <= #1 IDLE;
end else if (state == BUSY) begin
if (step == 1 | WZero ) begin
// if (step == 1 /* | WZero */) begin
// if (step == 1 | WZero ) begin
if (step == 1 /* | WZero */) begin
state <= #1 DONE;
end
step <= step - 1;

12
pipelined/testbench/testbench-fp.sv
View File

@ -792,8 +792,9 @@ always_comb begin
`CVTFPUNIT: ResFlg = Flg;
endcase
end
// check results on falling edge of clk
always @(negedge clk) begin
// check results on falling edge of clk
always @(negedge clk) begin
// check if the NaN value is good. IEEE754-2019 sections 6.3 and 6.2.3 specify:
@ -860,10 +861,11 @@ end
// check if result is correct
// - wait till the division result is done or one extra cylcle for early termination (to simulate the EM pipline stage)
if(~((Res === Ans | NaNGood | NaNGood === 1'bx) & (ResFlg === AnsFlg | AnsFlg === 5'bx))&~((DivBusy===1'b1)|DivStart)&(UnitVal !== `CVTINTUNIT)&(UnitVal !== `CMPUNIT)) begin
// if(~((Res === Ans | NaNGood | NaNGood === 1'bx) & (ResFlg === AnsFlg | AnsFlg === 5'bx))&~((DivBusy===1'b1)|DivStart)&(UnitVal !== `CVTINTUNIT)&(UnitVal !== `CMPUNIT)) begin
if(~((Res === Ans | NaNGood | NaNGood === 1'bx) & (ResFlg === AnsFlg | AnsFlg === 5'bx))&(DivDone | (TEST != "sqrt" & TEST != "div"))&(UnitVal !== `CVTINTUNIT)&(UnitVal !== `CMPUNIT)) begin
errors += 1;
$display("There is an error in %s", Tests[TestNum]);
$display("inputs: %h %h %h\nSrcA: %h\n Res: %h %h\n Ans: %h %h", X, Y, Z, SrcA, Res, ResFlg, Ans, AnsFlg);
$display("Error in %s", Tests[TestNum]);
$display("inputs: %h %h %h\nSrcA: %h\n Res: %h %h\n Expected: %h %h", X, Y, Z, SrcA, Res, ResFlg, Ans, AnsFlg);
$stop;
end