436 Commits

Author	SHA1	Message	Date
slmnemo	354d447269	Changed testbench to use fopen instead of opening and closing uartfile whenever writing	2024-04-20 16:56:54 -07:00
Quswar Abid	1b18568d87	the fix Rose provided in meeting	2024-04-17 09:39:21 -07:00
Kunlin Han	29c19d9cb4	Add system function through DPI to avoid missing support in Verilator.	2024-04-16 11:23:00 -07:00
Rose Thompson	1eb1beed95	Fixed merge conflict bug in the last pull request.	2024-04-16 10:32:24 -05:00
Rose Thompson	9fe86712d8	Merge branch 'main' into wsim_verilator	2024-04-16 09:07:50 -05:00
David Harris	160162c98a	Merge pull request #728 from Karl-Han/verilator_getenv ... Add support for getenvval as wrapper for Verilator's getenv	2024-04-15 17:55:34 -06:00
slmnemo	39ae26a897	Added documentation for known Verilator hierarchy bug	2024-04-15 15:58:09 -07:00
slmnemo	4b80457f3e	Fixed issue with Verilator hierarchical referencing by changing module names, moved run-imperas-linux to correct directory	2024-04-12 21:58:20 -07:00
slmnemo	342c99d6ea	Rearranged uart_logger block to only generate if UART is supported	2024-04-12 21:30:33 -07:00
Kunlin Han	eeb5c59143	Remove unnecessary sig and avoid uninitialized signal inside always block.	2024-04-12 16:06:10 -07:00
Kunlin Han	4d9de94029	Add support for getenvval as wrapper for Verilator's getenv.	2024-04-12 14:59:04 -07:00
David Harris	60e70c1986	Fixed testbench-fp replication length for regression-wally --testfloat. Changed regression-wally to expect -- in named arguments.	2024-04-08 05:57:18 -07:00
David Harris	d182a2925e	Fixed bug in testbench_fp for XLEN > FLEN	2024-04-07 05:40:18 -07:00
Rose Thompson	bb072fba84	Fixed the buildroot issue.	2024-04-06 18:25:53 -05:00
Rose Thompson	46fdfde7ec	Removed unnecessary display from testbench.	2024-04-06 16:10:18 -05:00
Rose Thompson	8885c32f7c	Merge branch 'main' of https://github.com/openhwgroup/cvw	2024-04-06 15:55:00 -05:00
David Harris	e8111da88a	Removed unused old regression-wally	2024-04-06 13:47:44 -07:00
David Harris	6b844a2e6e	Added GUI support and removed unused wave files	2024-04-06 13:43:06 -07:00
David Harris	3c855e3e90	Passing arguments to buildroot, not yet checking result correctly	2024-04-06 11:42:41 -07:00
David Harris	b3f007ec7f	Working on buildroot in regression	2024-04-06 11:11:22 -07:00
David Harris	ac9a21873d	Pass TEST to testbench with +TEST=<name> rather than -G TEST=<name> so that we don't have to recompile for every new test	2024-04-06 10:34:21 -07:00
David Harris	9ee7544d3c	TestFloat running; normal testbench broken	2024-04-06 09:28:07 -07:00
David Harris	4b19f6d542	testfloat running through wsim; moved lint, regression, wsim to bin directory so we don't need ./	2024-04-06 08:22:39 -07:00
slmnemo	d107a42e8c	Replaced rewrite command with system rm command for uart file. Fixed comment on line 573	2024-04-05 21:39:41 -07:00
slmnemo	2fcae601a9	Replaced funky rewrite call with file removal	2024-04-05 20:59:08 -07:00
David Harris	7b56809323	wsim runs a Questa sim	2024-04-05 19:08:14 -07:00
slmnemo	3ee25c8936	Merged testbench changes	2024-04-05 17:20:03 -07:00
slmnemo	5378b61eb2	Added UART output file buildroot_uart.out for Linux test 'buildroot'.	2024-04-05 17:18:03 -07:00
Rose Thompson	23e51e7277	starting on functional coverage for fence.i.	2024-04-04 15:44:57 -05:00
David Harris	ccd0e9cd0c	Clean up testbench-fp for Verilator	2024-04-03 17:26:41 -07:00
David Harris	ae8d581f4e	Started implementing Verilator for testfloat	2024-04-03 17:09:19 -07:00
Divya2030	aa6eacbce5	Merge branch 'openhwgroup:main' into main	2024-04-03 10:40:30 -07:00
Divya2030	135f3b6f8f	vcs testbench	2024-04-03 10:39:02 -07:00
David Harris	8755966f50	Incorporated Kunlin's Verilator hack so testbench runs 110x faster. Isolated within ifdef VERILATOR to make it easier to remove when Verilator issue 4967 is resolved	2024-04-03 07:23:02 -07:00
David Harris	8741b01818	Merge branch 'main' of https://github.com/openhwgroup/cvw into dev	2024-04-03 06:51:24 -07:00
David Harris	929eb0430c	Testbench uses posedge control signals to speed up Verilator	2024-04-03 06:51:18 -07:00
Rose Thompson	c11d7ea55e	Fixed bug in the testbench which did not allow external memory to work correctly.	2024-04-01 10:59:40 -05:00
Rose Thompson	4a7c16990f	Merge branch 'main' of https://github.com/openhwgroup/cvw	2024-03-28 13:45:12 -05:00
Rose Thompson	35eba468f7	Removed unused testbench-xcelium.sv.	2024-03-28 13:43:26 -05:00
Rose Thompson	b87cdd49a3	Merge pull request #690 from davidharrishmc/dev ... fcvt.h.l fixes, removed delays	2024-03-28 13:42:41 -05:00
Rose Thompson	081cf5be55	Fixed the CacheHit logger bug.	2024-03-28 13:40:01 -05:00
David Harris	4eb7de7381	Removed Zfh tests from wally-riscv-arch-test now that they are available in riscv-arch-test	2024-03-26 13:58:59 -07:00
David Harris	0caab3c0c9	Removed delays from cacheLRU and testbench	2024-03-25 12:20:25 -07:00
David Harris	690338b758	Incorporated fixed fcvt.h.l* instructions; they now run in the testbench	2024-03-25 06:08:27 -07:00
Jordan Carlin	d580d7af5d	Merge branch 'main' of https://github.com/openhwgroup/cvw	2024-03-23 17:56:23 -07:00
Jordan Carlin	fd97108dc3	Update testbench-fp to support Zfa in FPU modules	2024-03-23 17:55:59 -07:00
David Harris	bae52cf13d	Merge pull request #678 from Karl-Han/latest ... [Resolved Conflict] Remove all #delay from non-testbench	2024-03-23 15:18:04 -07:00
Kunlin Han	22b59138f0	Remove all #delay from non-testbench.	2024-03-16 11:20:32 -07:00
David Harris	b4a914a6e3	Commented out fcvt.h.l tests that don't run on fh_arch64gc arch64zfh; added testbench feature to print when the program jumps to address 0, presumably a bad trap handler	2024-03-14 21:53:30 -07:00
David Harris	9ff9f9e0ae	Updated wally-riscv-arch-test to be able to compile zfh and zfa tests. This caused a change in startup code, so certain reference_output results needed to change to compensate. Also commented out fcvtmod test in Zfa that fails because Sail produces the wrong expected value.	2024-03-14 19:03:57 -07:00