Ross Thompson
2f2a4f4500
Fixed subtle and infrequenct bug.
...
Loading buildroot at 483M instructions started with a spill + ITLBMiss. The spillsupport logic allowed transition to the second access only after the bus/cache completed the first operation. However the BusStall was suppressed if ITLBMissF occurs resulting in the spillfsm advancing to the second operation. Now the spill logic also takes in ITLBMissF and prevents the early transition to the second access.
2022-02-11 10:46:06 -06:00
David Harris
15fb7fee60
Cleaned up synthesis warnings
2022-02-11 01:15:16 +00:00
Ross Thompson
fc6dc52618
Fixed bugs in ifu spills and missing reset on bus data register.
2022-02-10 18:11:57 -06:00
Ross Thompson
9ad4523b9d
Updated wave files to reflect recent changes.
2022-02-10 17:52:19 -06:00
Ross Thompson
f23817bf69
Replacement policy cleanup.
2022-02-10 11:42:40 -06:00
Ross Thompson
411997010b
Replacement policy cleanup.
2022-02-10 11:40:10 -06:00
Ross Thompson
382d5fab0f
Cleanup.
2022-02-10 11:27:15 -06:00
Ross Thompson
3a0af5d9e9
Cleanup + critical path optimizations.
2022-02-10 11:11:16 -06:00
Ross Thompson
fc68c2f09a
Cache name clarifications.
2022-02-10 10:50:17 -06:00
Ross Thompson
e00d404154
More cache cleanup.
2022-02-10 10:43:37 -06:00
Ross Thompson
65803ebe98
structural muxes.
2022-02-09 19:36:21 -06:00
Ross Thompson
2a989e6d05
More cache cleanup.
2022-02-09 19:29:15 -06:00
Ross Thompson
3b8ad3f7c7
Cleaned up comments.
2022-02-09 19:21:35 -06:00
Ross Thompson
911ee36b22
Removed all possilbe paths to PreSelAdr from TrapM.
2022-02-09 19:20:10 -06:00
Ross Thompson
327a05c9d8
Added commented out commands to generate saif file from vsim.
2022-02-09 18:40:45 -06:00
Ross Thompson
01126535db
Annotated the final changes required to move sram address off the critial path.
2022-02-08 18:17:31 -06:00
Ross Thompson
7133e790ea
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-02-08 17:52:15 -06:00
Ross Thompson
498388c636
Cache cleanup write enables.
2022-02-08 17:52:09 -06:00
Ross Thompson
8a49ec90d0
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-02-08 15:43:18 -06:00
Ross Thompson
e0a605e95d
Cleanup IFU.
2022-02-08 14:54:53 -06:00
Ross Thompson
d1d014bf1d
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-02-08 14:47:15 -06:00
Ross Thompson
13561c67bd
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-02-08 14:22:19 -06:00
Ross Thompson
cecbb3362d
rv32e works for now. Still need to optimize.
2022-02-08 14:21:55 -06:00
Ross Thompson
39149c618f
Moved some muxes back into the bp.
2022-02-08 14:17:44 -06:00
David Harris
3e16730226
RAM simplification
2022-02-08 20:15:23 +00:00
Ross Thompson
d5d9bb9d4d
Temporary commit which gets the no branch predictor implementation working.
2022-02-08 14:13:55 -06:00
David Harris
c07584bb70
rv32e config update
2022-02-08 17:59:50 +00:00
Ross Thompson
c2377eaaf4
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-02-08 11:36:30 -06:00
Ross Thompson
3cd067ac6a
Finished merge.
2022-02-08 11:36:24 -06:00
David Harris
9ad3f26365
Restored E tests to makefrag
2022-02-08 16:41:11 +00:00
Ross Thompson
492c1473f3
Preparing to make a major change to the cache's write enables.
2022-02-08 09:47:01 -06:00
David Harris
e5097e67d4
Fixed TIM tests; rv32e test still failing
2022-02-08 15:24:37 +00:00
David Harris
e9a519a228
Patching up testbench; fixed false passing, but rv32ic and rv32e tests now fail
2022-02-08 12:40:02 +00:00
David Harris
096242a6d8
Merged TIM and regular testbenches. RV32e now working and back in regression.
2022-02-08 12:18:13 +00:00
David Harris
72c2166223
Lab 3 file cleanup
2022-02-08 10:26:37 +00:00
Ross Thompson
190d619940
cachefsm cleanup.
2022-02-07 22:09:56 -06:00
Ross Thompson
ca459a5915
Removed VDWriteEnable.
2022-02-07 21:59:18 -06:00
Ross Thompson
494802b2e1
more partial cleanup of fsm and write enables.
2022-02-07 17:41:56 -06:00
Ross Thompson
23a60d9875
Progress towards simplifying the cache's write enables.
2022-02-07 17:23:09 -06:00
Ross Thompson
fcd43ea004
more cleanup.
2022-02-07 13:29:19 -06:00
Ross Thompson
e72d54ea98
More cachefsm cleanup.
2022-02-07 13:19:37 -06:00
Ross Thompson
a6a7779ec0
More cachefsm cleanup.
2022-02-07 12:30:27 -06:00
Ross Thompson
7f732eb571
More cachefsm cleanup.
2022-02-07 11:16:20 -06:00
Ross Thompson
be67c4d559
More cachefsm cleanup.
2022-02-07 11:12:28 -06:00
Ross Thompson
f1781c6bc8
More cachefsm cleanup.
2022-02-07 10:54:22 -06:00
Ross Thompson
b89ce18473
Cache cleanup.
2022-02-07 10:43:58 -06:00
Ross Thompson
6f4a321d31
More cachfsm cleanup.
2022-02-07 10:33:50 -06:00
David Harris
60c3cdad3a
Reverted cache change
2022-02-07 14:47:20 +00:00
David Harris
d0c40cca7a
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2022-02-07 14:43:31 +00:00
David Harris
c21eb67a07
Cache syntax cleanup
2022-02-07 14:43:24 +00:00
Ross Thompson
8bcaadda6b
More cachefsm cleanup.
2022-02-06 21:50:44 -06:00
Ross Thompson
347e9228f8
started cachefsm cleanup.
2022-02-06 21:39:38 -06:00
Kip Macsai-Goren
38b75e85a0
added new tests to make and testbench
2022-02-06 19:47:22 +00:00
David Harris
0feb624bab
Added E tests to wally-riscv-arch-test rv32i_m/I and fixed cyclic path in rv32e configuration
2022-02-06 01:22:40 +00:00
bbracker
27dd363a85
remove sporadic tabs from tests.vh so that it is now only spaces
2022-02-05 23:07:38 +00:00
bbracker
fc2e3d1fbf
remove rv32e from regression because it is broken; goes with previous commit
2022-02-05 23:05:21 +00:00
Ross Thompson
308cc34d6f
Added config to allow using the save/restore or replay implementation to handle sram clocked read delay.
2022-02-04 23:49:07 -06:00
David Harris
0dd8c719ad
Modified regression to use proper rv32e test name, but rv32e_wally32e still isn't passing due to loop exceeding iteration limit
2022-02-05 05:35:51 +00:00
David Harris
f7d6939d9b
Merged buildroot do files into wally-pipelined do files, added work suffixes so buildroot regression won't fail due to file conflicts
2022-02-05 05:28:40 +00:00
David Harris
581fbb7d13
Modified wally-pipelined-batch.do to handle buildroot
2022-02-05 05:07:07 +00:00
Ross Thompson
1766c0f5ba
Removed unused ports from caches and buses.
2022-02-04 22:52:51 -06:00
Ross Thompson
dce4f8a0e5
Cleanup.
2022-02-04 22:40:51 -06:00
Ross Thompson
53551ab533
Moved the hwdata mux back into the busdp.
2022-02-04 22:39:13 -06:00
Ross Thompson
34cf77797a
Merged together the two sub cache line read muxes.
...
One mux was used for loads and the other for eviction.
2022-02-04 22:30:04 -06:00
David Harris
23868a33bc
Temporarily changed rv32e config to use TIM, but it still fails. Added rv32e tests.
2022-02-05 04:16:18 +00:00
Ross Thompson
c846368537
Moved the sub cache line read logic to lsu/ifu.
2022-02-04 20:42:53 -06:00
Ross Thompson
f6f0539e10
Got separate module for the sub cache line read.
2022-02-04 20:23:09 -06:00
Ross Thompson
ceb2cc30b9
Second optimization of save/restore.
2022-02-04 14:35:12 -06:00
Ross Thompson
498c2b589a
Optimization of cache save/restore.
2022-02-04 14:21:04 -06:00
Ross Thompson
83fdedcec6
Working first cut of the cache changes moving the replay to a save/restore.
...
The current implementation is too expensive costing (tag+linelen)*numway flip flops and muxes.
2022-02-04 13:31:32 -06:00
David Harris
16b5fee795
RV32e tests
2022-02-04 14:30:36 +00:00
David Harris
14c1d86953
rv32e
2022-02-04 01:56:30 +00:00
David Harris
1c049f1f67
renamed configs
2022-02-03 23:36:41 +00:00
David Harris
c3122ce214
sram1rw cleanup
2022-02-03 18:03:22 +00:00
David Harris
0e1d784b60
sram1rw cleanup
2022-02-03 17:50:23 +00:00
David Harris
eb8dd5e7d7
cachereplacementpolicy cleanup
2022-02-03 17:19:14 +00:00
David Harris
5f7326368e
cachereplacementpolicy cleanup
2022-02-03 17:18:48 +00:00
David Harris
9b6a4d1d52
cacheway cleanup
2022-02-03 16:52:22 +00:00
David Harris
7a8cc5ef21
cacheway cleanup
2022-02-03 16:33:01 +00:00
David Harris
0fbc32204c
cacheway cleanup
2022-02-03 16:07:55 +00:00
David Harris
c22f7eb11c
cacheway cleanup
2022-02-03 16:00:57 +00:00
David Harris
e92461159d
cache cleanup
2022-02-03 15:36:11 +00:00
Ross Thompson
4a5aa43716
Merge branch 'makefiles' into main
2022-02-03 08:33:50 -06:00
Ross Thompson
55382be055
Completed makefile updates to accelerate the generation of memfiles. There are two makefiles in the
...
regression directory. Makefile calls the submakefiles for generating elf files.
The second makefile-memfiles generates the memfiles, addr, and label files.
2022-02-03 08:32:48 -06:00
Ross Thompson
9da3223ce6
Manged to get all the tests compiled and converted to memfiles using new makefiles.
2022-02-03 00:00:15 -06:00
Ross Thompson
41978d59e4
Quick patch to regression-wally to "fix" rv32ic.
2022-02-02 19:24:24 -06:00
Ross Thompson
789cf13be6
broken makefiles.
2022-02-02 19:15:11 -06:00
Ross Thompson
ac19cd48a4
Broken makefiles.
2022-02-02 19:14:42 -06:00
David Harris
9e0055cbb9
More config file cleanup; 32ic tests broken
2022-02-03 01:08:34 +00:00
David Harris
bdf1a8ba73
changed DMEM and IMEM configurations to support BUS/TIM/CACHE
2022-02-03 00:41:09 +00:00
David Harris
172a02551b
Removed Busybear and Buildroot Configuration
2022-02-02 20:32:22 +00:00
David Harris
c12407ba6a
Removed Busybear dependencies
2022-02-02 20:28:21 +00:00
Ross Thompson
f3c2e426b1
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-02-02 11:41:54 -06:00
Ross Thompson
2f7cf2bc7f
Fixed testbench so coremark stops.
2022-02-02 11:37:48 -06:00
David Harris
761dae72fe
Config file & wally-riscv-arch-test cleanup
2022-02-02 16:35:52 +00:00
Ross Thompson
88a408b3e6
Added helpful signals to wavefile.
...
Makefile for tests now creates the function address to name mapping files.
The function name and test name are included in the wave file.
2022-02-02 10:15:54 -06:00
Ross Thompson
ae36931bb2
Added correct stop condition for coremark.
2022-02-02 09:53:51 -06:00
Ross Thompson
2d8b0aa650
Modified makefiles to generate function address to name mappings for modelsim.
2022-02-01 18:25:03 -06:00
Ross Thompson
058b368a22
Improved function_radix to not printout warnings when no valid function is found.
2022-02-01 18:03:09 -06:00
Ross Thompson
138b17a399
Setup the main regression test to be able to handle coremark.
2022-02-01 17:00:11 -06:00
Ross Thompson
910d16b642
More cleanup of IFU.
2022-02-01 14:32:27 -06:00
Ross Thompson
a9b4f9b1e7
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-02-01 10:50:38 -06:00
Ross Thompson
99bb281944
Updated fpga's bootloader to reflect the changes to the gpio address change.
2022-02-01 10:43:24 -06:00
Ross Thompson
dce9ee12b4
IFU and LSU now share the same busdp module.
2022-01-31 16:25:41 -06:00
Ross Thompson
a04aa283cb
partial ifu cleanup.
2022-01-31 16:08:53 -06:00
Ross Thompson
b05abc1795
cleanup.
2022-01-31 13:29:04 -06:00
Ross Thompson
c1311ca56a
Fixed modelsim warning with linux simulation.
2022-01-31 12:57:02 -06:00
Ross Thompson
d2ab17e1af
Repaired linux-wave.do
2022-01-31 12:54:18 -06:00
Ross Thompson
3475e142a5
Repaired wavefile and fixed modelsim warning.
2022-01-31 12:34:17 -06:00
Ross Thompson
1476a79ea2
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-01-31 12:17:37 -06:00
Ross Thompson
fa8914a830
Cleanup busdp.
2022-01-31 12:17:07 -06:00
Ross Thompson
7c3d6bbdb4
Moved lsu virtual memory logic into separate module.
2022-01-31 11:56:03 -06:00
Ross Thompson
e35a8299ec
Encapsulated dtim.
2022-01-31 11:23:55 -06:00
Ross Thompson
dbe40856a2
Removed unused signals in the LSU.
2022-01-31 10:35:35 -06:00
Ross Thompson
bfbc31d184
Moved atomic logic to own module.
2022-01-31 10:28:12 -06:00
Ross Thompson
ef770fd183
Encapsulated the bus data path into a separate module.
2022-01-31 10:15:48 -06:00
Kip Macsai-Goren
1077cf08b0
added machine info test that uses new test library
2022-01-31 05:54:43 +00:00
David Harris
2d112698b7
Replaced || and && with | and &
2022-01-31 01:07:35 +00:00
Ross Thompson
d52c5b0393
LSU and IFU cleanup.
2022-01-28 15:26:06 -06:00
Ross Thompson
de0bef4f5b
Updated wave.do to match the ifu/lsu changes.
2022-01-28 14:37:15 -06:00
Ross Thompson
147d71fd46
Clean up of mmu instances in IFU and LSU.
2022-01-28 14:02:05 -06:00
Ross Thompson
4a8d0cb981
Moved spills to own module.
2022-01-28 13:40:35 -06:00
Ross Thompson
7fedc6b878
Cleaned up the InstrMisalignedFault.
2022-01-28 13:19:24 -06:00
Ross Thompson
1bb8d36308
Moved all instr/load/storeamo faults to mmu with the exception of instr misaligned fault.
2022-01-27 17:11:27 -06:00
Ross Thompson
d7d7c1cb7d
Relocated the misalignment faults.
2022-01-27 16:03:00 -06:00
David Harris
87aa0724a2
IFU cleanup
2022-01-27 17:18:55 +00:00
David Harris
218ff3e25d
IFU cleanup
2022-01-27 16:41:57 +00:00
David Harris
1c22077841
Optimized out second adder from IFU for PC+2
2022-01-27 16:06:24 +00:00
David Harris
62e5c7fd13
Comments in LSU code about restructuring
2022-01-27 15:53:59 +00:00
Ross Thompson
9a9dfcae40
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-01-27 08:45:33 -06:00
Ross Thompson
d38ab9d2d7
Increased number of concurrent tests.
2022-01-27 08:45:25 -06:00
David Harris
975c0e72c8
Set up rv32emc config
2022-01-27 14:37:58 +00:00
Ross Thompson
75c33bc6c9
BPPredWrongM needs to be 0 when there is no branch predictor. BPPredWRongM is only used when there is an icacheflush.
2022-01-27 07:59:59 -06:00
Ross Thompson
b961b104e0
Added colors to regression script to make it easy to pick out success from fail.
2022-01-26 22:40:32 -06:00
Ross Thompson
c3a78553be
Removed mux in PCNextF logic. Minor IFU improvements.
2022-01-26 22:33:26 -06:00
Ross Thompson
23c4ba2777
1. Modified the cache so it can handle the reset delay internally. This removes the mux from the IFU.
...
2. Removed the write address delay from simpleram.sv
3. Fixed rv32tim and rv32ic mode to handle missalignment correctly.
4. Added imperas32i and imperas32c to rv32tim mode.
2022-01-26 18:23:39 -06:00
Ross Thompson
2c982dca03
IFU simplifications.
2022-01-26 13:54:59 -06:00
David Harris
c6adb7b6b1
Updated configs to fix GPIO address to match FU540
2022-01-26 18:16:34 +00:00
David Harris
c60bb68bff
Testgen working for Lab 2
2022-01-26 18:01:51 +00:00
Ross Thompson
728e46a794
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-01-25 19:21:04 -06:00
David Harris
22c84dcd80
simpleram simplification
2022-01-25 19:46:13 +00:00
David Harris
8bf73d0eb3
simpleram simplification
2022-01-25 19:40:07 +00:00
David Harris
f07123ff0f
simpleram simplification
2022-01-25 18:26:31 +00:00
David Harris
7ac44cb3fc
simpleram address simplification
2022-01-25 18:17:33 +00:00
David Harris
5eb71a3bbe
simpleram address simplification
2022-01-25 18:00:50 +00:00
David Harris
d9888c91a6
simpleram clk and reset simplification
2022-01-25 17:34:15 +00:00
David Harris
5cb879129e
Start of IFU cleanup
2022-01-25 17:31:53 +00:00
Ross Thompson
4d4d9ac8cf
Added spill support back into the IROM IFU.
2022-01-21 15:50:54 -06:00
Ross Thompson
4ecc2d029a
Changed the IROM and DTIM memories to behave like edge-triggered srams.
2022-01-21 15:42:54 -06:00
David Harris
c2c7351b24
erge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2022-01-21 00:12:18 +00:00
David Harris
0bb63e9ad1
Fixed path to riscvOVPsimPlus
2022-01-21 00:12:14 +00:00
Ross Thompson
ec44774c77
Factored out InstrValidNotFlushedM from each csr*.sv to csr.sv
2022-01-20 16:39:54 -06:00
David Harris
ca1f7ce5d3
Renamed wallypipelinedhart to wallypipelinedcore
2022-01-20 16:02:08 +00:00
David Harris
0d0aa59e48
Removed imperas tests from makefile for now
2022-01-20 14:51:56 +00:00
David Harris
f420e63ed0
Added top-level make clean
2022-01-20 14:17:26 +00:00
David Harris
537cb1d1e1
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2022-01-20 00:04:27 +00:00
Ross Thompson
05ebadacad
Added PCNextF and PostSpillInstrRawF to ila.
2022-01-19 14:05:14 -06:00
David Harris
f966d98e56
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2022-01-19 00:26:34 +00:00
Ross Thompson
5cf686429d
Merged in the debug ila updates.
2022-01-18 17:29:21 -06:00
Ross Thompson
2508b9d35a
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-01-18 17:19:59 -06:00
Ross Thompson
fdc17f5017
Updated CSR modules to prevent writting the registers when flushing. This only effects architecture writes not side effect writes.
2022-01-18 17:19:33 -06:00
David Harris
1a21e7f011
riscvsingle reparittioned to match Ch4
2022-01-17 16:57:32 +00:00
David Harris
de7b9c127e
Added E extension, and downloaded riscv-dv and embench-iot to addins
2022-01-17 14:42:59 +00:00
David Harris
5842d780a7
Defined rv32e and rv32emc configs
2022-01-17 14:01:01 +00:00
David Harris
8b62130070
lsu cleanup down to 346 lines
2022-01-15 01:19:44 +00:00
David Harris
b967bcede2
LSU Cleanup
2022-01-15 01:11:17 +00:00
David Harris
f7f3882cb8
Moved Dcache into bus block
2022-01-15 00:39:07 +00:00
David Harris
d9e8d16bbe
Renamed LSUStall to LSUStallM
2022-01-15 00:24:16 +00:00
David Harris
b0263012e8
LSU cleanup
2022-01-15 00:11:30 +00:00
David Harris
4c5962095e
LSU cleanup
2022-01-15 00:03:03 +00:00
David Harris
37bf5347cf
LSU cleanup
2022-01-14 23:55:27 +00:00
Ross Thompson
dd1ebb75f0
Fixed spillthreshold warning.
2022-01-14 17:23:39 -06:00
Ross Thompson
9d2a79f180
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-01-14 17:16:53 -06:00
David Harris
380e990def
moved fp to tests
2022-01-14 23:05:59 +00:00
David Harris
291deb5c39
LSU partitioning
2022-01-14 23:02:28 +00:00
David Harris
36d49a8a74
Moved fp tests from testbench to tests/fp
2022-01-14 23:00:46 +00:00
Ross Thompson
db519a0dca
Cleanup IFU comments.
2022-01-14 15:06:30 -06:00
Ross Thompson
a70e12ad75
Optimization in the ifu. Please note this optimization is not strictly correct,
...
but is possible. See comments in the ifu source code for details.
2022-01-14 12:16:48 -06:00
Ross Thompson
a549079672
More ifu cleanup.
2022-01-14 11:19:12 -06:00
Ross Thompson
ce937a35a8
Added tim only test to regression-wally. Minor cleanup to ifu.
2022-01-14 11:13:06 -06:00
James E. Stine
115ea7dbb0
Update to TestFloat for scripts so can run automatically once
...
TestFloat/Softfloat is compiled. Slight change to the README as well.
2022-01-14 09:25:37 -06:00
Ross Thompson
5726b5b640
Added support for logic memory in the IFU and LSU. This disables the bus interface. Peripherals do not work. Also requires using testbench-harvard.sv. I hope to merge this testbench with the main testbench.sv soon.
2022-01-13 22:21:43 -06:00
Ross Thompson
9f7e3f147b
Partial local dtim in lsu configuration.
2022-01-13 17:50:31 -06:00
David Harris
d356a0d29f
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2022-01-13 21:46:00 +00:00
David Harris
e3f6c398b5
Mixed C and assembly language test cases; SRT initial version passing tests
2022-01-13 21:45:54 +00:00
Ross Thompson
0b06fa12ef
Merge branch 'testDivInterruptInterlock' into main
2022-01-13 11:21:48 -06:00
Ross Thompson
93cb24476f
Fixed interger divide so it can be interrupted.
2022-01-13 11:16:50 -06:00
Ross Thompson
4bcabd1a55
Removed unused inputs to hptw.
2022-01-13 11:04:48 -06:00
Ross Thompson
654a33bf92
Fixed bug in the lsu's write back data. If an AMO was uncached it would not be corrected executed because the write data to the bus would not include the amoalu.
2022-01-12 17:41:39 -06:00
Ross Thompson
861450c4d6
Fixed support to allow spills and no icache.
2022-01-12 17:25:16 -06:00
Ross Thompson
000d713cb5
Better solution to the integer divider interrupt interaction.
2022-01-12 14:22:18 -06:00
Ross Thompson
26fb09c868
Added additional fsm to ILA.
2022-01-12 14:17:16 -06:00
Ross Thompson
6eb2f37ce4
Possible fix for the TrapM DTLBMiss suppression.
2022-01-12 14:17:16 -06:00
Ross Thompson
6b483e621d
If a trap occurs concurrent with a I/DTLB miss the interlock fsm incorrectly goes into the states to handle the TLB miss.
...
This commit fixes this bug by keeping the interlock fsm in the T0_READY state on TrapM.
2022-01-12 14:17:16 -06:00
Ross Thompson
48c036a923
Oups. My hack for DivE interrupt prevention was wrong.
2022-01-12 14:17:16 -06:00
Ross Thompson
796316495d
Hack "fix" to prevent interrupt from occuring during an integer divide.
...
This is not the desired solution but will allow continued debuging of linux.
2022-01-12 14:17:16 -06:00
Ross Thompson
ecd3912900
Set rv32ic to not use icache.
2022-01-12 14:10:09 -06:00
Ross Thompson
2ed052f152
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-01-12 13:29:19 -06:00
Ross Thompson
87485f9f64
Improve wavefile by adding performance counters.
2022-01-12 10:53:29 -06:00
Kip Macsai-Goren
c99456d5e7
Fixed PMA regions, Added passing PMA tests to regression
2022-01-10 22:08:26 +00:00
