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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main

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This commit is contained in:
David Harris 2022-01-13 21:46:00 +00:00
commit d356a0d29f
15 changed files with 125 additions and 92 deletions
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29
fpga/constraints/debug2.xdc
View File

@ -84,9 +84,9 @@ set_property port_width 4 [get_debug_ports u_ila_0/probe16]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe16]
connect_debug_port u_ila_0/probe16 [get_nets [list {wallypipelinedsoc/uncore/sdc.SDC/sd_top/r_DAT_Q[0]} {wallypipelinedsoc/uncore/sdc.SDC/sd_top/r_DAT_Q[1]} {wallypipelinedsoc/uncore/sdc.SDC/sd_top/r_DAT_Q[2]} {wallypipelinedsoc/uncore/sdc.SDC/sd_top/r_DAT_Q[3]} ]]
create_debug_port u_ila_0 probe
set_property port_width 32 [get_debug_ports u_ila_0/probe17]
set_property port_width 4 [get_debug_ports u_ila_0/probe17]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe17]
connect_debug_port u_ila_0/probe17 [get_nets [list {wallypipelinedsoc/hart/lsu/dcache.dcache/cachefsm/CurrState[0]} {wallypipelinedsoc/hart/lsu/dcache.dcache/cachefsm/CurrState[1]} {wallypipelinedsoc/hart/lsu/dcache.dcache/cachefsm/CurrState[2]} {wallypipelinedsoc/hart/lsu/dcache.dcache/cachefsm/CurrState[3]} {wallypipelinedsoc/hart/lsu/dcache.dcache/cachefsm/CurrState[4]} {wallypipelinedsoc/hart/lsu/dcache.dcache/cachefsm/CurrState[5]} {wallypipelinedsoc/hart/lsu/dcache.dcache/cachefsm/CurrState[6]} {wallypipelinedsoc/hart/lsu/dcache.dcache/cachefsm/CurrState[7]} {wallypipelinedsoc/hart/lsu/dcache.dcache/cachefsm/CurrState[8]} {wallypipelinedsoc/hart/lsu/dcache.dcache/cachefsm/CurrState[9]} {wallypipelinedsoc/hart/lsu/dcache.dcache/cachefsm/CurrState[10]} {wallypipelinedsoc/hart/lsu/dcache.dcache/cachefsm/CurrState[11]} {wallypipelinedsoc/hart/lsu/dcache.dcache/cachefsm/CurrState[12]} {wallypipelinedsoc/hart/lsu/dcache.dcache/cachefsm/CurrState[13]} {wallypipelinedsoc/hart/lsu/dcache.dcache/cachefsm/CurrState[14]} {wallypipelinedsoc/hart/lsu/dcache.dcache/cachefsm/CurrState[15]} {wallypipelinedsoc/hart/lsu/dcache.dcache/cachefsm/CurrState[16]} {wallypipelinedsoc/hart/lsu/dcache.dcache/cachefsm/CurrState[17]} {wallypipelinedsoc/hart/lsu/dcache.dcache/cachefsm/CurrState[18]} {wallypipelinedsoc/hart/lsu/dcache.dcache/cachefsm/CurrState[19]} {wallypipelinedsoc/hart/lsu/dcache.dcache/cachefsm/CurrState[20]} {wallypipelinedsoc/hart/lsu/dcache.dcache/cachefsm/CurrState[21]} {wallypipelinedsoc/hart/lsu/dcache.dcache/cachefsm/CurrState[22]} {wallypipelinedsoc/hart/lsu/dcache.dcache/cachefsm/CurrState[23]} {wallypipelinedsoc/hart/lsu/dcache.dcache/cachefsm/CurrState[24]} {wallypipelinedsoc/hart/lsu/dcache.dcache/cachefsm/CurrState[25]} {wallypipelinedsoc/hart/lsu/dcache.dcache/cachefsm/CurrState[26]} {wallypipelinedsoc/hart/lsu/dcache.dcache/cachefsm/CurrState[27]} {wallypipelinedsoc/hart/lsu/dcache.dcache/cachefsm/CurrState[28]} {wallypipelinedsoc/hart/lsu/dcache.dcache/cachefsm/CurrState[29]} {wallypipelinedsoc/hart/lsu/dcache.dcache/cachefsm/CurrState[30]} {wallypipelinedsoc/hart/lsu/dcache.dcache/cachefsm/CurrState[31]} ]]
connect_debug_port u_ila_0/probe17 [get_nets [list {wallypipelinedsoc/hart/lsu/dcache.dcache/cachefsm/CurrState[0]} {wallypipelinedsoc/hart/lsu/dcache.dcache/cachefsm/CurrState[1]} {wallypipelinedsoc/hart/lsu/dcache.dcache/cachefsm/CurrState[2]} {wallypipelinedsoc/hart/lsu/dcache.dcache/cachefsm/CurrState[3]} ]]
create_debug_port u_ila_0 probe
set_property port_width 64 [get_debug_ports u_ila_0/probe18]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe18]
@ -444,9 +444,9 @@ set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe98]
connect_debug_port u_ila_0/probe98 [get_nets [list wallypipelinedsoc/hart/hzu/FlushW ]]
create_debug_port u_ila_0 probe
set_property port_width 24 [get_debug_ports u_ila_0/probe99]
set_property port_width 4 [get_debug_ports u_ila_0/probe99]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe99]
connect_debug_port u_ila_0/probe99 [get_nets [list {wallypipelinedsoc/hart/ifu/icache.icache/cachefsm/CurrState[0]} {wallypipelinedsoc/hart/ifu/icache.icache/cachefsm/CurrState[1]} {wallypipelinedsoc/hart/ifu/icache.icache/cachefsm/CurrState[2]} {wallypipelinedsoc/hart/ifu/icache.icache/cachefsm/CurrState[3]} {wallypipelinedsoc/hart/ifu/icache.icache/cachefsm/CurrState[4]} {wallypipelinedsoc/hart/ifu/icache.icache/cachefsm/CurrState[5]} {wallypipelinedsoc/hart/ifu/icache.icache/cachefsm/CurrState[6]} {wallypipelinedsoc/hart/ifu/icache.icache/cachefsm/CurrState[7]} {wallypipelinedsoc/hart/ifu/icache.icache/cachefsm/CurrState[8]} {wallypipelinedsoc/hart/ifu/icache.icache/cachefsm/CurrState[9]} {wallypipelinedsoc/hart/ifu/icache.icache/cachefsm/CurrState[10]} {wallypipelinedsoc/hart/ifu/icache.icache/cachefsm/CurrState[11]} {wallypipelinedsoc/hart/ifu/icache.icache/cachefsm/CurrState[12]} {wallypipelinedsoc/hart/ifu/icache.icache/cachefsm/CurrState[13]} {wallypipelinedsoc/hart/ifu/icache.icache/cachefsm/CurrState[14]} {wallypipelinedsoc/hart/ifu/icache.icache/cachefsm/CurrState[15]} {wallypipelinedsoc/hart/ifu/icache.icache/cachefsm/CurrState[16]} {wallypipelinedsoc/hart/ifu/icache.icache/cachefsm/CurrState[17]} {wallypipelinedsoc/hart/ifu/icache.icache/cachefsm/CurrState[18]} {wallypipelinedsoc/hart/ifu/icache.icache/cachefsm/CurrState[19]} {wallypipelinedsoc/hart/ifu/icache.icache/cachefsm/CurrState[20]} {wallypipelinedsoc/hart/ifu/icache.icache/cachefsm/CurrState[21]} {wallypipelinedsoc/hart/ifu/icache.icache/cachefsm/CurrState[22]} {wallypipelinedsoc/hart/ifu/icache.icache/cachefsm/CurrState[23]}]]
connect_debug_port u_ila_0/probe99 [get_nets [list {wallypipelinedsoc/hart/ifu/icache.icache/cachefsm/CurrState[0]} {wallypipelinedsoc/hart/ifu/icache.icache/cachefsm/CurrState[1]} {wallypipelinedsoc/hart/ifu/icache.icache/cachefsm/CurrState[2]} {wallypipelinedsoc/hart/ifu/icache.icache/cachefsm/CurrState[3]}]]
create_debug_port u_ila_0 probe
@ -570,3 +570,24 @@ set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe122]
connect_debug_port u_ila_0/probe122 [get_nets [list {wallypipelinedsoc/hart/ifu/PCPF[0]} {wallypipelinedsoc/hart/ifu/PCPF[1]} {wallypipelinedsoc/hart/ifu/PCPF[2]} {wallypipelinedsoc/hart/ifu/PCPF[3]} {wallypipelinedsoc/hart/ifu/PCPF[4]} {wallypipelinedsoc/hart/ifu/PCPF[5]} {wallypipelinedsoc/hart/ifu/PCPF[6]} {wallypipelinedsoc/hart/ifu/PCPF[7]} {wallypipelinedsoc/hart/ifu/PCPF[8]} {wallypipelinedsoc/hart/ifu/PCPF[9]} {wallypipelinedsoc/hart/ifu/PCPF[10]} {wallypipelinedsoc/hart/ifu/PCPF[11]} {wallypipelinedsoc/hart/ifu/PCPF[12]} {wallypipelinedsoc/hart/ifu/PCPF[13]} {wallypipelinedsoc/hart/ifu/PCPF[14]} {wallypipelinedsoc/hart/ifu/PCPF[15]} {wallypipelinedsoc/hart/ifu/PCPF[16]} {wallypipelinedsoc/hart/ifu/PCPF[17]} {wallypipelinedsoc/hart/ifu/PCPF[18]} {wallypipelinedsoc/hart/ifu/PCPF[19]} {wallypipelinedsoc/hart/ifu/PCPF[20]} {wallypipelinedsoc/hart/ifu/PCPF[21]} {wallypipelinedsoc/hart/ifu/PCPF[22]} {wallypipelinedsoc/hart/ifu/PCPF[23]} {wallypipelinedsoc/hart/ifu/PCPF[24]} {wallypipelinedsoc/hart/ifu/PCPF[25]} {wallypipelinedsoc/hart/ifu/PCPF[26]} {wallypipelinedsoc/hart/ifu/PCPF[27]} {wallypipelinedsoc/hart/ifu/PCPF[28]} {wallypipelinedsoc/hart/ifu/PCPF[29]} {wallypipelinedsoc/hart/ifu/PCPF[30]} {wallypipelinedsoc/hart/ifu/PCPF[31]} {wallypipelinedsoc/hart/ifu/PCPF[32]} {wallypipelinedsoc/hart/ifu/PCPF[33]} {wallypipelinedsoc/hart/ifu/PCPF[34]} {wallypipelinedsoc/hart/ifu/PCPF[35]} {wallypipelinedsoc/hart/ifu/PCPF[36]} {wallypipelinedsoc/hart/ifu/PCPF[37]} {wallypipelinedsoc/hart/ifu/PCPF[38]} {wallypipelinedsoc/hart/ifu/PCPF[39]} {wallypipelinedsoc/hart/ifu/PCPF[40]} {wallypipelinedsoc/hart/ifu/PCPF[41]} {wallypipelinedsoc/hart/ifu/PCPF[42]} {wallypipelinedsoc/hart/ifu/PCPF[43]} {wallypipelinedsoc/hart/ifu/PCPF[44]} {wallypipelinedsoc/hart/ifu/PCPF[45]} {wallypipelinedsoc/hart/ifu/PCPF[46]} {wallypipelinedsoc/hart/ifu/PCPF[47]} {wallypipelinedsoc/hart/ifu/PCPF[48]} {wallypipelinedsoc/hart/ifu/PCPF[49]} {wallypipelinedsoc/hart/ifu/PCPF[50]} {wallypipelinedsoc/hart/ifu/PCPF[51]} {wallypipelinedsoc/hart/ifu/PCPF[52]} {wallypipelinedsoc/hart/ifu/PCPF[53]} {wallypipelinedsoc/hart/ifu/PCPF[54]} {wallypipelinedsoc/hart/ifu/PCPF[55]} ]]
create_debug_port u_ila_0 probe
set_property port_width 3 [get_debug_ports u_ila_0/probe123]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe123]
connect_debug_port u_ila_0/probe123 [get_nets [list {wallypipelinedsoc/hart/ifu/busfsm/BusCurrState[0]} {wallypipelinedsoc/hart/ifu/busfsm/BusCurrState[1]} {wallypipelinedsoc/hart/ifu/busfsm/BusCurrState[2]} ]]
create_debug_port u_ila_0 probe
set_property port_width 1 [get_debug_ports u_ila_0/probe124]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe124]
connect_debug_port u_ila_0/probe124 [get_nets [list wallypipelinedsoc/hart/ifu/SpillSupport.CurrState[0] ]]
create_debug_port u_ila_0 probe
set_property port_width 3 [get_debug_ports u_ila_0/probe125]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe125]
connect_debug_port u_ila_0/probe125 [get_nets [list {wallypipelinedsoc/hart/lsu/busfsm/BusCurrState[0]} {wallypipelinedsoc/hart/lsu/busfsm/BusCurrState[1]} {wallypipelinedsoc/hart/lsu/busfsm/BusCurrState[2]} ]]
create_debug_port u_ila_0 probe
set_property port_width 3 [get_debug_ports u_ila_0/probe126]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe126]
connect_debug_port u_ila_0/probe126 [get_nets [list {wallypipelinedsoc/hart/lsu/MEM_VIRTMEM.interlockfsm/InterlockCurrState[0]} {wallypipelinedsoc/hart/lsu/MEM_VIRTMEM.interlockfsm/InterlockCurrState[1]} {wallypipelinedsoc/hart/lsu/MEM_VIRTMEM.interlockfsm/InterlockCurrState[2]} ]]

2
pipelined/config/rv32ic/wally-config.vh
View File

@ -52,7 +52,7 @@
`define MEM_DTIM 1
`define MEM_DCACHE 0
`define MEM_IROM 1
`define MEM_ICACHE 1
`define MEM_ICACHE 0
`define MEM_VIRTMEM 0
`define VECTORED_INTERRUPTS_SUPPORTED 1

2
pipelined/regression/wally-coremark.do
View File

@ -38,7 +38,7 @@ vsim workopt
mem load -startaddress 268435456 -endaddress 268566527 -filltype value -fillradix hex -filldata 0 /testbench/dut/uncore/ram/ram/RAM
#add log -recursive /*
do wave.do
run -all
#run 21400

127
pipelined/regression/wave.do
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File diff suppressed because one or more lines are too long

2
pipelined/src/hazard/hazard.sv
View File

@ -62,7 +62,7 @@ module hazard(
assign StallFCause = CSRWritePendingDEM & ~(TrapM | RetM | BPPredWrongE);
assign StallDCause = (LoadStallD | StoreStallD | MDUStallD | CSRRdStallD | FPUStallD | FStallD) & ~(TrapM | RetM | BPPredWrongE); // stall in decode if instruction is a load/mul/csr dependent on previous
assign StallECause = DivBusyE | FDivBusyE;
assign StallECause = (DivBusyE | FDivBusyE) & ~(TrapM);
assign StallMCause = 0;
assign StallWCause = LSUStall | IFUStallF;

6
pipelined/src/ifu/ifu.sv
View File

@ -130,7 +130,7 @@ module ifu (
assign PCNextFMux = SelNextSpill ? PCFp2[11:0] : PCNextF[11:0];
assign PCFMux = SelSpill ? PCFp2 : PCF;
assign Spill = &PCF[$clog2(`ICACHE_LINELENINBITS/32)+1:1];
assign Spill = &PCF[$clog2(SPILLTHRESHOLD)+1:1];
typedef enum {STATE_SPILL_READY, STATE_SPILL_SPILL} statetype;
(* mark_debug = "true" *) statetype CurrState, NextState;
@ -159,7 +159,7 @@ module ifu (
flopenr #(16) SpillInstrReg(.clk(clk),
.en(SpillSave),
.reset(reset),
.d(InstrRawF[15:0]),
.d(`MEM_ICACHE ? InstrRawF[15:0] : InstrRawF[31:16]),
.q(SpillDataLine0));
assign PostSpillInstrRawF = Spill ? {InstrRawF[15:0], SpillDataLine0} : InstrRawF;
@ -226,6 +226,7 @@ module ifu (
// 3. wire pass-through
localparam integer WORDSPERLINE = `MEM_ICACHE ? `ICACHE_LINELENINBITS/`XLEN : 1;
localparam integer SPILLTHRESHOLD = `MEM_ICACHE ? `ICACHE_LINELENINBITS/32 : 1;
localparam integer LOGWPL = `MEM_ICACHE ? $clog2(WORDSPERLINE) : 1;
localparam integer LINELEN = `MEM_ICACHE ? `ICACHE_LINELENINBITS : `XLEN;
localparam integer WordCountThreshold = `MEM_ICACHE ? WORDSPERLINE - 1 : 0;
@ -360,6 +361,7 @@ module ifu (
assign PCNextF = {UnalignedPCNextF[`XLEN-1:1], 1'b0}; // hart-SPEC p. 21 about 16-bit alignment
// *** double check this enable. It cannot be correct.
flopenl #(`XLEN) pcreg(clk, reset, ~StallF & ~ICacheStallF, PCNextF, `RESET_VECTOR, PCF);
// branch and jump predictor

7
pipelined/src/lsu/interlockfsm.sv
View File

@ -55,7 +55,7 @@ module interlockfsm
STATE_T5_ITLB_MISS,
STATE_T7_DITLB_MISS} statetype;
statetype InterlockCurrState, InterlockNextState;
(* mark_debug = "true" *) statetype InterlockCurrState, InterlockNextState;
always_ff @(posedge clk)
@ -64,7 +64,8 @@ module interlockfsm
always_comb begin
case(InterlockCurrState)
STATE_T0_READY: if(~ITLBMissF & DTLBMissM & AnyCPUReqM) InterlockNextState = STATE_T3_DTLB_MISS;
STATE_T0_READY: if (TrapM) InterlockNextState = STATE_T0_READY;
else if(~ITLBMissF & DTLBMissM & AnyCPUReqM) InterlockNextState = STATE_T3_DTLB_MISS;
else if(ITLBMissF & ~DTLBMissM & ~AnyCPUReqM) InterlockNextState = STATE_T4_ITLB_MISS;
else if(ITLBMissF & ~DTLBMissM & AnyCPUReqM) InterlockNextState = STATE_T5_ITLB_MISS;
else if(ITLBMissF & DTLBMissM & AnyCPUReqM) InterlockNextState = STATE_T7_DITLB_MISS;
@ -97,7 +98,7 @@ module interlockfsm
always_comb begin
InterlockStall = 1'b0;
case(InterlockCurrState)
STATE_T0_READY: if(DTLBMissM | ITLBMissF) InterlockStall = 1'b1;
STATE_T0_READY: if((DTLBMissM | ITLBMissF) & ~TrapM) InterlockStall = 1'b1;
STATE_T3_DTLB_MISS: InterlockStall = 1'b1;
STATE_T4_ITLB_MISS: InterlockStall = 1'b1;
STATE_T5_ITLB_MISS: InterlockStall = 1'b1;

9
pipelined/src/lsu/lsu.sv
View File

@ -142,9 +142,9 @@ module lsu
hptw hptw(.clk, .reset, .SATP_REGW, .PCF, .IEUAdrM,
.ITLBMissF(ITLBMissF & ~TrapM),
.DTLBMissM(DTLBMissM & ~TrapM),
.MemRWM, .PTE, .PageType, .ITLBWriteF, .DTLBWriteM,
.PTE, .PageType, .ITLBWriteF, .DTLBWriteM,
.HPTWReadPTE(ReadDataM),
.DCacheStall, .HPTWAdr, .HPTWRead, .HPTWSize, .AnyCPUReqM);
.DCacheStall, .HPTWAdr, .HPTWRead, .HPTWSize);
// arbiter between IEU and hptw
@ -374,7 +374,10 @@ module lsu
assign LocalLSUBusAdr = SelUncachedAdr ? LSUPAdrM : DCacheBusAdr ;
assign LSUBusAdr = ({{`PA_BITS-LOGWPL{1'b0}}, WordCount} << $clog2(`XLEN/8)) + LocalLSUBusAdr;
assign PreLSUBusHWDATA = ReadDataLineSetsM[WordCount];
assign LSUBusHWDATA = SelUncachedAdr ? WriteDataM : PreLSUBusHWDATA; // *** why is this not FinalWriteDataM? which does not work.
// exclude the subword write for uncached. We don't read the data first so we cannot
// select the subword by masking. Subword write also exists inside the uncore to
// suport subword masking for i/o. I'm not sure if this is necessary.
assign LSUBusHWDATA = SelUncachedAdr ? FinalAMOWriteDataM : PreLSUBusHWDATA;
if (`XLEN == 32) assign LSUBusSize = SelUncachedAdr ? LSUFunct3M : 3'b010;
else assign LSUBusSize = SelUncachedAdr ? LSUFunct3M : 3'b011;

3
pipelined/src/mmu/hptw.sv
View File

@ -36,10 +36,8 @@ module hptw
input logic [`XLEN-1:0] SATP_REGW, // includes SATP.MODE to determine number of levels in page table
input logic [`XLEN-1:0] PCF, IEUAdrM, // addresses to translate
(* mark_debug = "true" *) input logic ITLBMissF, DTLBMissM, // TLB Miss
input logic [1:0] MemRWM, // 10 = read, 01 = write
input logic [`XLEN-1:0] HPTWReadPTE, // page table entry from LSU
input logic DCacheStall, // stall from LSU
input logic AnyCPUReqM,
output logic [`XLEN-1:0] PTE, // page table entry to TLBs
output logic [1:0] PageType, // page type to TLBs
(* mark_debug = "true" *) output logic ITLBWriteF, DTLBWriteM, // write TLB with new entry
@ -73,7 +71,6 @@ module hptw
// Extract bits from CSRs and inputs
assign SvMode = SATP_REGW[`XLEN-1:`XLEN-`SVMODE_BITS];
assign BasePageTablePPN = SATP_REGW[`PPN_BITS-1:0];
assign MemWrite = MemRWM[0];
assign TLBMiss = (DTLBMissM | ITLBMissF);
// Determine which address to translate

3
pipelined/src/muldiv/intdivrestoring.sv
View File

@ -36,6 +36,7 @@ module intdivrestoring (
input logic clk,
input logic reset,
input logic StallM,
input logic TrapM,
input logic DivSignedE, W64E,
input logic DivE,
//input logic [`XLEN-1:0] SrcAE, SrcBE,
@ -116,7 +117,7 @@ module intdivrestoring (
//////////////////////////////
always_ff @(posedge clk)
if (reset) begin
if (reset | TrapM) begin
state <= IDLE;
end else if (DivStartE) begin
step <= 1;

6
pipelined/src/muldiv/muldiv.sv
View File

@ -41,8 +41,9 @@ module muldiv (
output logic [`XLEN-1:0] MDUResultW,
// Divide Done
output logic DivBusyE,
output logic DivE,
// hazards
input logic StallM, StallW, FlushM, FlushW
input logic StallM, StallW, FlushM, FlushW, TrapM
);
logic [`XLEN-1:0] MDUResultM;
@ -50,7 +51,6 @@ module muldiv (
logic [`XLEN-1:0] QuotM, RemM;
logic [`XLEN*2-1:0] ProdM;
logic DivE;
logic DivSignedE;
logic W64M;
@ -61,7 +61,7 @@ module muldiv (
// Start a divide when a new division instruction is received and the divider isn't already busy or finishing
assign DivE = MDUE & Funct3E[2];
assign DivSignedE = ~Funct3E[0];
intdivrestoring div(.clk, .reset, .StallM, .DivSignedE, .W64E, .DivE,
intdivrestoring div(.clk, .reset, .StallM, .TrapM, .DivSignedE, .W64E, .DivE,
.ForwardedSrcAE, .ForwardedSrcBE, .DivBusyE, .QuotM, .RemM);
// Result multiplexer

4
pipelined/src/privileged/privileged.sv
View File

@ -39,7 +39,7 @@ module privileged (
output logic [`XLEN-1:0] PrivilegedNextPCM,
output logic RetM, TrapM,
output logic ITLBFlushF, DTLBFlushM,
input logic InstrValidM, CommittedM,
input logic InstrValidM, CommittedM, DivE,
input logic FRegWriteM, LoadStallD,
input logic BPPredDirWrongM,
input logic BTBPredPCWrongM,
@ -230,7 +230,7 @@ module privileged (
.PCM,
.InstrMisalignedAdrM, .IEUAdrM,
.InstrM,
.InstrValidM, .CommittedM,
.InstrValidM, .CommittedM, .DivE,
.TrapM, .MTrapM, .STrapM, .UTrapM, .RetM,
.InterruptM,
.ExceptionM,

6
pipelined/src/privileged/trap.sv
View File

@ -46,7 +46,7 @@ module trap (
input logic [`XLEN-1:0] PCM,
input logic [`XLEN-1:0] InstrMisalignedAdrM, IEUAdrM,
input logic [31:0] InstrM,
input logic InstrValidM, CommittedM,
input logic InstrValidM, CommittedM, DivE,
output logic TrapM, MTrapM, STrapM, UTrapM, RetM,
output logic InterruptM,
output logic ExceptionM,
@ -71,7 +71,9 @@ module trap (
assign SIntGlobalEnM = (PrivilegeModeW == `U_MODE) | ((PrivilegeModeW == `S_MODE) & STATUS_SIE); // if in lower priv mode, or if S ints enabled and not in higher priv mode 3.1.9
assign PendingIntsM = ((MIP_REGW & MIE_REGW) & ({12{MIntGlobalEnM}} & 12'h888)) | ((SIP_REGW & SIE_REGW) & ({12{SIntGlobalEnM}} & 12'h222));
assign PendingInterruptM = (|PendingIntsM) & InstrValidM;
assign InterruptM = PendingInterruptM & ~CommittedM;
assign InterruptM = PendingInterruptM & ~(CommittedM); // *** RT. temporary hack to prevent integer division from having an interrupt during divide.
// ideally this should be disabled for all but the first cycle. However I'm not familar with the internals of the integer divider. This should (could) be an issue for
// floating point and integer multiply.
//assign ExceptionM = TrapM;
assign ExceptionM = Exception1M;
// *** as of 7/17/21, the system passes with this definition of ExceptionM as being all traps and fails if ExceptionM = Exception1M

2
pipelined/src/uncore/uncore.sv
View File

@ -191,7 +191,7 @@ module uncore (
// mux could also include external memory
// AHB Read Multiplexer
assign HRDATA = ({`XLEN{HSELRamD}} & HREADRam) |
({`XLEN{HSELEXTD}} & HRDATAEXT) |
({`XLEN{HSELEXTD}} & HRDATAEXT) |
({`XLEN{HSELCLINTD}} & HREADCLINT) |
({`XLEN{HSELPLICD}} & HREADPLIC) |
({`XLEN{HSELGPIOD}} & HREADGPIO) |

9
pipelined/src/wally/wallypipelinedhart.sv
View File

@ -87,11 +87,12 @@ module wallypipelinedhart (
logic PCSrcE;
logic CSRWritePendingDEM;
logic DivBusyE;
logic DivE;
logic LoadStallD, StoreStallD, MDUStallD, CSRRdStallD;
logic SquashSCW;
// floating point unit signals
logic [2:0] FRM_REGW;
logic [4:0] RdM, RdW;
logic [4:0] RdM, RdW;
logic FStallD;
logic FWriteIntE;
logic [`XLEN-1:0] FWriteDataE;
@ -321,7 +322,7 @@ module wallypipelinedhart (
.InstrM, .CSRReadValW, .PrivilegedNextPCM,
.RetM, .TrapM,
.ITLBFlushF, .DTLBFlushM,
.InstrValidM, .CommittedM,
.InstrValidM, .CommittedM, .DivE,
.FRegWriteM, .LoadStallD,
.BPPredDirWrongM, .BTBPredPCWrongM,
.RASPredPCWrongM, .BPPredClassNonCFIWrongM,
@ -356,8 +357,8 @@ module wallypipelinedhart (
.clk, .reset,
.ForwardedSrcAE, .ForwardedSrcBE,
.Funct3E, .Funct3M, .MDUE, .W64E,
.MDUResultW, .DivBusyE,
.StallM, .StallW, .FlushM, .FlushW
.MDUResultW, .DivBusyE, .DivE,
.StallM, .StallW, .FlushM, .FlushW, .TrapM
);
end else begin // no M instructions supported
assign MDUResultW = 0;