Ross Thompson fdc17f5017 Updated CSR modules to prevent writting the registers when flushing. This only effects architecture writes not side effect writes.		2022-01-18 17:19:33 -06:00
..
config	Added tim only test to regression-wally. Minor cleanup to ifu.	2022-01-14 11:13:06 -06:00
fpu-testfloat/FMA/tbgen	Removed more generate statements	2022-01-05 16:25:08 +00:00
misc
regression	LSU Cleanup	2022-01-15 01:11:17 +00:00
src	Updated CSR modules to prevent writting the registers when flushing. This only effects architecture writes not side effect writes.	2022-01-18 17:19:33 -06:00
srt	Mixed C and assembly language test cases; SRT initial version passing tests	2022-01-13 21:45:54 +00:00
testbench	Moved Dcache into bus block	2022-01-15 00:39:07 +00:00