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  • 2b75e38239 Fix issues in parallel regression testing Jarred Allen 2021-02-01 23:29:03 -0500
  • c634b2f81e busybear: start adding CSR checking Noah Boorstin 2021-02-01 22:08:11 -0500
  • 94de3e9fb2 OSU FPU IP initial commit Brett Mathis 2021-02-01 19:33:43 -0600
  • ff88214730 busybear: change register file checking to only store register changed Noah Boorstin 2021-02-02 01:27:43 +0000
  • 416b3fc96c Add PCW checking Noah Boorstin 2021-02-01 23:57:06 +0000
  • 056b147b13 Renamed DCU to DMEM David Harris 2021-02-01 18:52:22 -0500
  • 84801213d6 Parallelize regression-wally.p Jarred Allen 2021-02-01 15:40:27 -0500
  • a432d607ce busybear: print warning when NOPing out instructions Noah Boorstin 2021-02-01 19:44:56 +0000
  • b7f63c1dc7 busybear: NOP out floating point instructions for now Noah Boorstin 2021-01-30 19:52:47 +0000
  • 4358f086be update busybear testbench to conform to new structure Noah Boorstin 2021-01-30 17:38:18 +0000
  • 396cea1ea7 Reorganized src hierarchically David Harris 2021-01-30 11:50:37 -0500
  • fc1fb94217 Working on reading instruction from TIM David Harris 2021-01-30 01:57:51 -0500
  • 61fd7c4499 Adding stalls for memory delays David Harris 2021-01-30 01:43:49 -0500
  • 9c81278f28 Added HCLK and HRESETn David Harris 2021-01-30 00:56:12 -0500
  • a357f2a0e7 Connected AHB bus to Uncore David Harris 2021-01-29 23:43:48 -0500
  • 73a584b223 Added SATP, PMPCFG0-3, PMPADDR0 CSRs for Linux team David Harris 2021-01-29 18:06:36 -0500
  • e700e404c9 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main David Harris 2021-01-29 17:29:01 -0500
  • 9a51bb27c3 Implemented adrdec for uncore David Harris 2021-01-29 17:28:53 -0500
  • 9eafdbe349 - Removed latch on CSRCReadValM in csrc.sv - Changed top level to wallypipelinedhart Teo Ene 2021-01-29 15:23:28 -0600
  • 8679e9aae3 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main Teo Ene 2021-01-29 15:04:51 -0600
  • 94b35ac47c Synth automatically globs all available verilog files now, instead of requiring manual file listing Teo Ene 2021-01-29 15:04:43 -0600
  • 8d4f5277d2 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main David Harris 2021-01-29 15:38:01 -0500
  • dc2443c55b Moving data memory to uncore David Harris 2021-01-29 15:37:51 -0500
  • 3d02d6f09f Added AHBW to rv32ic config file as well Teo Ene 2021-01-29 12:29:08 -0600
  • 194d5b55ab update busybear testbench to conform to new structure Noah Boorstin 2021-01-29 17:46:50 +0000
  • a94c09cad8 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main David Harris 2021-01-29 01:07:22 -0500
  • ed3cb83c10 Added ahblite bus interface unit David Harris 2021-01-29 01:07:17 -0500
  • dabb026104 busybear: lie about MISA to match OVP's MISA Noah Boorstin 2021-01-29 00:58:56 -0500
  • 8ab5879af5 busybear testbench: test on first 100k instrs Noah Boorstin 2021-01-29 00:13:14 -0500
  • 618c6e4813 Renamed modules in privileged unit David Harris 2021-01-28 23:21:12 -0500
  • fd2f854a69 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main David Harris 2021-01-28 21:40:57 -0500
  • 05b755958f Hint to optimize ifu David Harris 2021-01-28 21:40:48 -0500
  • 619dec1490 busybear: simulate first 10k instructions Noah Boorstin 2021-01-28 19:44:58 -0500
  • 4f84bd3c8f busybear: fix misaligned writing checking Noah Boorstin 2021-01-28 19:35:09 -0500
  • beb93e2508 busybear: add more test instructions Noah Boorstin 2021-01-28 16:41:37 -0500
  • 287cf4e5a6 oops forgot to add C.BEQZ, C.BNEZ checks to busybear testbench Noah Boorstin 2021-01-28 16:35:12 -0500
  • 91e9defd0a more of the same fixes Noah Boorstin 2021-01-28 16:26:15 -0500
  • 623d9feeab more misaligned read fixing Noah Boorstin 2021-01-28 16:13:10 -0500
  • 12c6006f07 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main David Harris 2021-01-28 15:44:14 -0500
  • fe0876027f Fixed floating signals in clint and ieu David Harris 2021-01-28 15:44:05 -0500
  • 405c9d90b5 busybear testbench: understand bytemask for writes Noah Boorstin 2021-01-28 15:42:47 -0500
  • 7a3f29b260 Make gdb output parser understand other varients of load/store Noah Boorstin 2021-01-28 15:35:41 -0500
  • ad5d4793b6 Fixed c.jr instruction improperly writing ra David Harris 2021-01-28 15:18:23 -0500
  • a4bac85ece busybear: ret is only 1 word Noah Boorstin 2021-01-28 14:47:40 -0500
  • 0befdfacec add speculative exception for compressed instructions Noah Boorstin 2021-01-28 14:40:35 -0500
  • 27142f0fef testbench now understands lw not aligned to 8 bytes Noah Boorstin 2021-01-28 13:33:22 -0500
  • a2598b2b30 busybear testbench: check for read data address also Noah Boorstin 2021-01-28 13:16:38 -0500
  • f2aea55def update busybear testbench to conform to new structure Noah Boorstin 2021-01-28 01:21:47 -0500
  • 206747b8b2 Busybear test now processes first 100 instrs correctly! Noah Boorstin 2021-01-28 01:16:39 -0500
  • 8f6994196a fix memory write address decoding for busybear tests Noah Boorstin 2021-01-28 01:04:56 -0500
  • f95d0690ca Created DCU and moved memdp into DCU David Harris 2021-01-28 01:03:12 -0500
  • be1d1886a9 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main David Harris 2021-01-28 00:22:11 -0500
  • a50b6c2a15 Provided PC + 2 or 4 (PCLink) for JAL David Harris 2021-01-28 00:22:05 -0500
  • 28fabb94ee update busybear testbench to conform to new structure Noah Boorstin 2021-01-27 23:42:19 -0500
  • 4df461ad77 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main David Harris 2021-01-27 22:49:55 -0500
  • 824014c5c0 Repartitioned with Instruction Fetch Unit, Integer Execution Unit David Harris 2021-01-27 22:49:47 -0500
  • c9baa70e26 update busybear testbench to conform to new structure Noah Boorstin 2021-01-27 12:54:09 -0500
  • 616afaba69 Moved privileged unit from datapath to hart David Harris 2021-01-27 07:46:52 -0500
  • e84fbd0a73 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main David Harris 2021-01-27 06:40:39 -0500
  • b88508ca11 Repartitioned datapath and controller into ieu David Harris 2021-01-27 06:40:26 -0500
  • 1195ebb468 show instruction assembly in waveform Noah Boorstin 2021-01-26 12:34:12 -0500
  • 6c567aab9a Update busybear tests to conform to new directory structure Noah Boorstin 2021-01-25 20:37:18 -0500
  • e92db93939 Fixed mem write checking Noah Boorstin 2021-01-25 20:06:13 -0500
  • 358393a1da fix speculation ignoring for PC fetching Noah Boorstin 2021-01-25 19:45:26 -0500
  • 1d9c741c00 Reset Vector moved to config file David Harris 2021-01-25 15:57:36 -0500
  • 4e0b13696b Added synth and PnR flow Teo Ene 2021-01-25 14:28:14 -0600
  • fa18052348 Added test configurations David Harris 2021-01-25 11:28:43 -0500
  • aea1c0cd2e small busybear testbench changes Noah Boorstin 2021-01-24 20:43:47 -0500
  • e7288716f7 Linux testbench works now Noah Boorstin 2021-01-24 17:10:00 -0500
  • 12a8f83025 Merge branch 'busybear' into main Noah Boorstin 2021-01-24 16:28:36 -0500
  • 815da0fb11 handle "zero" as 0 properly Noah Boorstin 2021-01-24 01:03:45 -0500
  • 5b23b22d9a Start on checking mem writes Noah Boorstin 2021-01-24 00:58:22 -0500
  • 2cbc01953e Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main David Harris 2021-01-24 00:52:06 -0500
  • bea0e1da78 Replaced parameters with macros for XLEN, MISA, other configuration, and renamed wally-params.sv to wally-config.vh David Harris 2021-01-23 10:48:12 -0500
  • 8cccfc698d Cleaned up regfile x0 tied to gnd David Harris 2021-01-23 10:22:20 -0500
  • 307b7688eb Initial checkin of UART David Harris 2021-01-23 10:19:09 -0500
  • b08b86f561 sucessfully simulate first 30 instructions Noah Boorstin 2021-01-23 19:01:44 -0500
  • a75d7e4555 More linux testbench fixes Noah Boorstin 2021-01-23 17:52:05 -0500
  • be62987dec Linux test now gets through first 8 instructions! Noah Boorstin 2021-01-23 16:42:17 -0500
  • 3905e77e54 Replaced parameters with macros for XLEN, MISA, other configuration, and renamed wally-params.sv to wally-config.vh David Harris 2021-01-23 10:48:12 -0500
  • 170c88bc06 Cleaned up regfile x0 tied to gnd David Harris 2021-01-23 10:22:20 -0500
  • 93f8c6f29e Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main David Harris 2021-01-23 10:19:28 -0500
  • 6b9c6223be Initial checkin of UART David Harris 2021-01-23 10:19:09 -0500
  • 18f6aa716e slightly more info on errors, add instruction decoding Noah Boorstin 2021-01-22 21:14:45 -0500
  • 3b16766fde change how testbench reads data Noah Boorstin 2021-01-22 20:27:01 -0500
  • 4c51a20634 change regfile to not hold state of x0 Noah Boorstin 2021-01-22 15:12:33 -0500
  • 2c8571aaac change regfile to not hold state of x0 Noah Boorstin 2021-01-22 15:11:55 -0500
  • e45f452f25 Start adding register checking Noah Boorstin 2021-01-22 15:05:58 -0500
  • 8104b93900 load instructions from file line by line Noah Boorstin 2021-01-22 14:11:17 -0500
  • e8132800d3 Start of gdb output parser Noah Boorstin 2021-01-22 13:57:58 -0500
  • 8c85f891f5 add scripts for generating instruction trace Noah Boorstin 2021-01-22 13:06:45 -0500
  • 40f0b1e328 More testbench setup work Noah Boorstin 2021-01-21 17:55:05 -0500
  • 795359576b copy testbench to modify for busybear Noah Boorstin 2021-01-21 16:17:34 -0500
  • f32c70e866 testgen-ADD-SUB working and testbench simualtes with new vectors for rv32 and rv64 David Harris 2021-01-20 01:04:28 -0500
  • e3a7fcb5f1 testgen-ADD-SUB initial untested David Harris 2021-01-19 22:58:56 -0500
  • 5479342d00 Initial testgen checkin David Harris 2021-01-19 13:09:56 -0500
  • 6595c7827f Changed to . notation for instantiation, cleaned up dmem David Harris 2021-01-18 20:16:53 -0500
  • 46d02d3818 cleanup David Harris 2021-01-18 00:42:40 -0500
  • 18fe5c7c93 Sped up exe2memfile.pl David Harris 2021-01-17 18:45:19 -0500
  • df4d79f8f8 Added exe2memfile.py David Harris 2021-01-16 15:09:06 -0500