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  • 99f2d24e05 Latest IE tests with timer interupts ushakya22 2021-04-08 17:53:39 -0400
  • d99b8f772e Merge from branch 'main' Jarred Allen 2021-04-08 17:19:34 -0400
  • e73e16e57a Created special test for driving the instruction spill error. Ross Thompson 2021-04-08 15:05:08 -0500
  • 1ee8feffe5 integrated peripheral testing into existing workflow bbracker 2021-04-08 15:31:39 -0400
  • 005f838b8d Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main bbracker 2021-04-08 14:28:25 -0400
  • 755e2e5771 merge testbench bbracker 2021-04-08 14:28:01 -0400
  • b7ebfd66ed Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main Katherine Parry 2021-04-08 18:06:51 +0000
  • 8549e457c1 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main David Harris 2021-04-08 14:04:09 -0400
  • 6b2868a8c7 restored testbench-imperas.sv David Harris 2021-04-08 14:04:01 -0400
  • 2ee015d53e Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main Katherine Parry 2021-04-08 18:03:57 +0000
  • f4cb92ae71 fixed FPU lint warnings Katherine Parry 2021-04-08 18:03:21 +0000
  • 27cb94e7af fixed FPU lint warnings Katherine Parry 2021-04-08 17:55:25 +0000
  • 72a64edfb8 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main ushakya22 2021-04-08 13:55:23 -0400
  • b0f6898ece Updates to WALLY-IE tests ushakya22 2021-04-08 13:54:42 -0400
  • ac8a111d61 merge conflict resolution David Harris 2021-04-08 13:53:56 -0400
  • 6a6ccca3c8 fixed sim-wally-32ic David Harris 2021-04-08 13:40:16 -0400
  • 14d2ad1e2d try to remove git-lfs stuff Noah Boorstin 2021-04-08 13:23:11 -0400
  • 3067e94b4b Update privileged testgen & helper script Domenico Ottolia 2021-04-08 05:14:07 -0400
  • 65abe13f4f Cause an Illegal Instruction Exception when attempting to write readonly CSRs Domenico Ottolia 2021-04-08 05:12:54 -0400
  • fc39535e4e Refactor TLB into multiple files Thomas Fleming 2021-04-08 03:24:10 -0400
  • c54aecde73 Provide attribution link for priority encoder Thomas Fleming 2021-04-08 03:05:06 -0400
  • 303c2c4839 Implement support for superpages Thomas Fleming 2021-04-08 02:44:59 -0400
  • 4322694f7a Switch to use RV64IC for the benchmarks. Still not working correctly with the icache. Ross Thompson 2021-04-07 19:12:43 -0500
  • 83d9aa3a50 MIE privilege tests with working timer interupt ushakya22 2021-04-07 04:09:09 -0400
  • fd5a1f3874 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main ushakya22 2021-04-07 04:06:54 -0400
  • 60cf38192b Add privileged tests to testbench Domenico Ottolia 2021-04-07 02:22:08 -0400
  • 465d3986b0 Add passing mtval and mepc tests Domenico Ottolia 2021-04-07 02:21:05 -0400
  • c91436d3b7 Merge branch 'icache_bp_bug' into tests Not sure this merge is right. Ross Thompson 2021-04-06 21:46:40 -0500
  • 98a04abe6c Merge remote-tracking branch 'refs/remotes/origin/tests' into tests Ross Thompson 2021-04-06 21:20:55 -0500
  • bff2d61a1f Steps to getting branch predictor benchmarks running. Ross Thompson 2021-04-06 21:20:51 -0500
  • bd8f1eea3c Fix another bug in icache Jarred Allen 2021-04-06 17:47:00 -0400
  • 3afc358974 Fix another bug in icache Jarred Allen 2021-04-06 12:48:42 -0400
  • 4ac4cf2aaa Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main ushakya22 2021-04-06 12:29:23 -0400
  • 284d583877 add busybear boot files with git-lfs Noah Boorstin 2021-04-05 19:38:43 -0400
  • 0e3f013212 busybear: reenable 'ruthless' CSR checking Noah Boorstin 2021-04-05 12:47:11 -0400
  • 38017e6aae declare memread signal bbracker 2021-04-05 08:13:01 -0400
  • a4c3afb847 PLIC claim reg side effects now check for memread signal bbracker 2021-04-05 08:03:14 -0400
  • 4a5aa5b202 plic subword access compliance bbracker 2021-04-04 23:10:33 -0400
  • e6a7353847 Added missing files in FPU Katherine Parry 2021-04-04 18:09:13 +0000
  • 31c6b2d01f Yee hoo first draft of PLIC plus self-checking tests bbracker 2021-04-04 06:40:53 -0400
  • 6b43381c38 Comment out fpu from hart until module exists Thomas Fleming 2021-04-03 22:34:11 -0400
  • dbd5a4320e Merge branch 'mmu' into main Thomas Fleming 2021-04-03 22:12:52 -0400
  • 8dfec29f7e Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main Thomas Fleming 2021-04-03 22:09:50 -0400
  • f4e5642c62 busybear: temporary stop after 800k instrs Noah Boorstin 2021-04-03 21:37:57 -0400
  • 1cbdaf1f05 Fix extraneous page fault stall Thomas Fleming 2021-04-03 21:28:24 -0400
  • 6a35308068 Virtual memory test now turns on virtual memory Thomas Fleming 2021-04-03 21:24:06 -0400
  • c95da7d11e Fix bug in icache Jarred Allen 2021-04-03 18:04:59 -0400
  • d7b1379ab8 Integrated FPU Katherine Parry 2021-04-03 20:52:26 +0000
  • d21006d048 Partial fix to the integer divide stall issue. Ross Thompson 2021-04-02 15:32:15 -0500
  • 362f6ea2e6 Minor cleanup James E. Stine 2021-04-02 08:20:44 -0500
  • 0595ae983f Put back imperas testbench until figure out why m_supported is running for rv64ic James E. Stine 2021-04-02 08:19:25 -0500
  • cff08adc3a Added some updates to divider - still not working all the time. Still a bug with signals within muldiv - specificaly MultDivE being modified during Execute stage. Seems to be triggered by ahblite signal. James E. Stine 2021-04-02 06:27:37 -0500
  • bfb4b051c6 Merge branch 'main' into mmu Thomas Fleming 2021-04-01 16:29:39 -0400
  • 350fe87119 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main Thomas Fleming 2021-04-01 16:24:06 -0400
  • 38a0199260 Merge branch 'mmu' of github.com:davidharrishmc/riscv-wally into mmu Thomas Fleming 2021-04-01 16:23:19 -0400
  • fdb20ee1cf Implement sfence.vma and fix tlb writing Thomas Fleming 2021-04-01 15:55:05 -0400
  • 498433f8bf Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main ushakya22 2021-04-01 15:49:00 -0400
  • 5afb255251 Begin changes to direct-mapped cache Jarred Allen 2021-04-01 13:55:21 -0400
  • df149d1be7 fixed minor bugs in localHistory Shreya Sanghai 2021-04-01 13:40:08 -0400
  • 0495195d68 Fixed some divide -still bug in AHB causing InstStall to deassert and next instruction to get into divide unit. Hope to fix soon. Divide seems to work if given enough time. James E. Stine 2021-04-01 12:30:37 -0500
  • 28a9c6ba56 added localHistoryPredictor ShreyaSanghai 2021-04-01 22:22:40 +0530
  • ee89b891a4 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main ushakya22 2021-04-01 02:04:57 -0400
  • bee984a126 d ushakya22 2021-04-01 02:04:02 -0400
  • b544526766 fixed bugs in global history to read latest GHRE Shreya Sanghai 2021-03-31 21:56:14 -0400
  • 7c364a26e9 Updated MISA in coremark_bare config file Teo Ene 2021-03-31 20:39:02 -0500
  • 75f58c4df5 busybear: temporarially stop checking CSRs Noah Boorstin 2021-03-31 14:14:32 -0400
  • 118e846ef7 busybear: clean up questa warnings Noah Boorstin 2021-03-31 13:41:40 -0400
  • 43532be770 busybear: clean up questa warnings Noah Boorstin 2021-03-31 13:41:40 -0400
  • 9172e52286 Corrected a number of bugs in the branch predictor. Added performance counters to individually track branches; jumps, jump register, jal, and jalr; return. jump and jump register are special cases of jal and jalr. Similarlly return is a special case of jalr. Also added counters to track if the branch direction was wrong, btb target wrong, or the ras target was wrong. Finally added one more counter to track if the BP incorrectly predicts a non-cfi instruction. Ross Thompson 2021-03-31 11:54:02 -0500
  • a64a37d702 Merge of main with the new icache and the branch predictor. I believe there is a bug in the icache with unaligned memory access. The second part of the access is incorrectly relying on the PCF being the address of the next two bytes of the instruction. However this is not always the case as the branch predictor can get the wrong target address. The icache needs to generate the +2 address internally. Ross Thompson 2021-03-30 23:18:20 -0500
  • 853ddeba15 Remove virtual memory tests from rv32i folder Thomas Fleming 2021-03-30 22:51:52 -0400
  • 77b8e27205 Disable 'always-on' virtual memory Thomas Fleming 2021-03-30 22:49:47 -0400
  • 56e256baa5 Extend lint-wally to lint both rv32 and rv64 Thomas Fleming 2021-03-30 22:42:28 -0400
  • eca2427f94 Merge remote-tracking branch 'origin/main' into main Thomas Fleming 2021-03-30 22:24:47 -0400
  • 7126ab7864 Complete basic page table walker Thomas Fleming 2021-03-30 22:19:27 -0400
  • 0994d03b28 Update virtual memory tests and move to separate folder Thomas Fleming 2021-03-30 22:18:29 -0400
  • f7cbaeb217 Add one more test to WALLY-CAUSE, and update privileged testgen Domenico Ottolia 2021-03-30 19:44:58 -0400
  • 6619a5f44f Add mcause tests to testbench Domenico Ottolia 2021-03-30 17:17:59 -0400
  • 61b19a0cd0 Update privileged tests generator Domenico Ottolia 2021-03-30 16:58:46 -0400
  • 351c71e812 Add all working mcause tests Domenico Ottolia 2021-03-30 16:54:54 -0400
  • a659cfec3f Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main ushakya22 2021-03-30 15:36:30 -0400
  • 6b9ae41302 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main ushakya22 2021-03-30 15:25:07 -0400
  • fbed5d658e privilege tests ushakya22 2021-03-30 15:23:47 -0400
  • 4db8708652 Second update to divide that didn't get in for some silly git reason James E. Stine 2021-03-30 14:21:45 -0500
  • 9c09ad55ad Initial push of rv64imc and appropriate testbench James E. Stine 2021-03-30 14:21:02 -0500
  • 2a308309e4 fixed some bugs with the RAS. Ross Thompson 2021-03-30 13:57:40 -0500
  • 631454ccf9 Merge branch 'cache2' into cache Jarred Allen 2021-03-30 13:32:33 -0400
  • 6e83ccc3c4 Comment out failing tests Jarred Allen 2021-03-30 13:07:26 -0400
  • 108f18e580 Merge branch 'cache' into main Jarred Allen 2021-03-30 12:56:19 -0400
  • 7ca57cc4fc Merge branch 'main' into cache Jarred Allen 2021-03-30 12:55:01 -0400
  • eefeae58fa Added WALLY-PIPELINE to make David Harris 2021-03-26 13:13:13 -0400
  • 8723fb916c Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main David Harris 2021-03-26 13:04:52 -0400
  • 637bba6509 Added fp test to testbench David Harris 2021-03-26 13:03:23 -0400
  • b5a1691c2b Merge branch 'main' into cache Noah Boorstin 2021-03-26 12:26:30 -0400
  • 339bd5d3eb Merge branch 'PPA' into main Shreya Sanghai 2021-03-25 20:35:21 -0400
  • cc988f420f removed minor bugs Shreya Sanghai 2021-03-25 20:29:50 -0400
  • 39bf2347bc Fix error when reading an instruction that crosses a line boundary Jarred Allen 2021-03-25 18:47:23 -0400
  • 139c2076a1 Removed PCW and InstrW from ifu ShreyaSanghai 2021-03-26 01:53:19 +0530
  • 32829bf7a1 Remove old icache Jarred Allen 2021-03-25 15:46:35 -0400
  • 5f4feb0ff1 Works for misaligned instructions not on line boundaries Jarred Allen 2021-03-25 15:42:17 -0400