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  • 857f59ab5c Now have global history working correctly. Ross Thompson 2021-06-01 10:57:43 -0500
  • ddbdd0d5a2 Modify muldiv.sv to handle W instructions for 64-bits James E. Stine 2021-05-31 23:27:42 -0400
  • f6c88666cf may have fixed the global branch history predictor. The solution required a completed rewrite and understanding of how the GHR needs to be speculatively updated and repaired. Ross Thompson 2021-05-31 16:11:12 -0500
  • 0fe63282f8 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main Kip Macsai-Goren 2021-05-31 11:01:15 -0400
  • 46a232b862 Cosmetic changes on integer divider James E. Stine 2021-05-31 09:16:30 -0400
  • 9954d16fc9 Add enhancements to integer divider including: - better comments - optimize FSM to end earlier - passes for 32-bit or 64-bit depending on parameter to intdiv James E. Stine 2021-05-31 09:12:21 -0400
  • 12c34c25f3 Modify elements of generics for LZD and shifter wrote for integer divider. James E. Stine 2021-05-31 08:36:19 -0400
  • 39ae743543 turns out I should not have tried renaming FStallD to FPUStallD because that name was already used! All the same it does feel weird to have two such signals floating around \(ah pun!\) bbracker 2021-05-28 23:11:37 -0400
  • 690815ca51 made priority encoder parameterizable Kip Macsai-Goren 2021-05-28 18:09:28 -0400
  • 8a035104ac It's a bit sloppy, but the global history predictor is working correctly now. There were two major bugs with the predictor. First the update mechanism was completely wrong. The PHT is updated with the GHR that was used to lookup the prediction. PHT[GHR] = Sat2(PHT[GHR], branch outcome). Second the GHR needs to be updated speculatively as the branch is predicted. This is important so that back to back branches' GHRs are not the same. The must be different to avoid aliasing. Speculation of the GHR update allows them to be different. On mis prediction the GHR must be reverted. This implementation is a bit sloppy with names and now the GHR recovery is performed. Updates to follow. Ross Thompson 2021-05-27 23:06:28 -0500
  • 778ba6bbf5 classify unit created and passes imperas tests Katherine Parry 2021-05-27 18:53:55 -0400
  • 1459d840ed All compare instructions pass imperas tests Katherine Parry 2021-05-27 15:23:28 -0400
  • 7e84c3f514 Updated benchmarking code. Ross Thompson 2021-05-27 11:48:29 -0500
  • 309e6c3dc1 FADD and FSUB imperas tests pass Katherine Parry 2021-05-26 12:33:33 -0400
  • bb99480fca delete old file for FPregfile James E. Stine 2021-05-26 09:13:09 -0500
  • 77260643eb Add regression test for fpadd James E. Stine 2021-05-26 09:12:37 -0500
  • e7190b0690 renamed top level FPU wires Katherine Parry 2021-05-25 20:04:34 -0400
  • 33cd133a65 completed mstatus test for rv32p, rv64p, updated testbench to reflect Kip Macsai-Goren 2021-05-25 15:44:52 -0400
  • 45e7628e90 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main Kip Macsai-Goren 2021-05-25 15:28:19 -0400
  • fec40a1b75 fixed bug with icache miss spill fsm branch. Ross Thompson 2021-05-25 14:26:22 -0500
  • bb5404e14a Update FPregfile to use more compact code and better structure for ease in reading James E. Stine 2021-05-25 13:21:59 -0500
  • 063e458ff0 Merge remote-tracking branch 'refs/remotes/origin/main' into main Ross Thompson 2021-05-24 23:25:36 -0500
  • 16e037b8e9 Fixed bug in the two bit sat counter branch predictor. The SRAM needs to be read enabled by StallF. Ross Thompson 2021-05-24 23:24:54 -0500
  • 8ae43a15d4 partially complete MSTATUS test of sd, xs, fs, mie, mpp, mpie, sie, spie bitfields Kip Macsai-Goren 2021-05-24 20:59:26 -0400
  • c4f3f2f783 Minor cosmetic elements on div.sv James E. Stine 2021-05-24 19:30:28 -0500
  • 295263e122 Mod for DIV/REM instruction and update to div.sv unit James E. Stine 2021-05-24 19:29:13 -0500
  • f755827c90 slightly more path independence for using verilator bbracker 2021-05-24 18:11:56 -0400
  • 920dd7bd8d Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main bbracker 2021-05-24 17:09:14 -0400
  • b4bc4b7ee2 peripheral testing standardization bbracker 2021-05-24 17:08:40 -0400
  • c5310e85c1 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main Ross Thompson 2021-05-24 14:28:41 -0500
  • 90d5fdba04 FMV.X.D imperas test passes Katherine Parry 2021-05-24 14:44:30 -0400
  • 65632cb7c9 Fixed minor bug in instruction class decoding. Ross Thompson 2021-05-24 13:41:14 -0500
  • 72f77656a3 Fixed bug with instruction classification. The class decoder was incorretly labeling jalr acting as both jalr and jr (no link). Ross Thompson 2021-05-24 12:37:16 -0500
  • 8bf411c640 Updated branch predictor tests/benchmarks. Ross Thompson 2021-05-24 11:13:33 -0500
  • 6f38b7633c Update header for FPadd James E. Stine 2021-05-24 08:28:16 -0500
  • 70968a4ec3 FSD and FLD imperas tests pass Katherine Parry 2021-05-23 18:33:14 -0400
  • 846553ac7d improved PLIC test organization bbracker 2021-05-21 15:13:02 -0400
  • e70136ec78 Minor testbench updates to rv64icfd James E. Stine 2021-05-21 09:41:21 -0500
  • 23769e36a5 Update to testbench-imperase for rv64icfd James E. Stine 2021-05-21 09:28:44 -0500
  • fed3b30557 Update to FLD/FSD testbench James E. Stine 2021-05-21 09:26:55 -0500
  • c89d3e01bb Update to rv64icfd wally-config to run through FP tests James E. Stine 2021-05-21 09:22:17 -0500
  • 4db7f3065c FMV.D.X imperas test passes Katherine Parry 2021-05-20 22:18:33 -0400
  • 06af239e6c FMV.D.X imperas test passes Katherine Parry 2021-05-20 22:17:59 -0400
  • 1d3db5ead5 small bit of busybear debug progress bbracker 2021-05-19 20:18:00 -0400
  • bf6337f2f7 plic implementation optimizations bbracker 2021-05-19 18:10:48 +0000
  • 979a9bf037 commented out MSTATUS test bbracker 2021-05-19 12:38:01 -0400
  • 304e70d3ae Update rv64icfd batch script James E. Stine 2021-05-18 16:01:53 -0500
  • 44dc665fc5 Mod to config to properly add FP stuff - for icfd test. Should not change regression test through Imperas as just mod to testbench (add tests64d/tests64f but remove from MISA) James E. Stine 2021-05-18 13:48:44 -0500
  • e4d51ebef5 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main bbracker 2021-05-18 14:33:40 -0400
  • c495fc71f1 changed lint script to use absolute path for verilator because cron jobs stink at using paths bbracker 2021-05-18 14:33:22 -0400
  • 26531f2634 fixed rv64mmu makefile David Harris 2021-05-18 14:25:55 -0400
  • 5da159d17e Removed rv64wally David Harris 2021-05-18 14:08:46 -0400
  • 4d264c6f61 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main David Harris 2021-05-18 14:01:19 -0400
  • a885d44129 commented changes to imperas makefiles bbracker 2021-05-18 13:34:48 -0400
  • 9464c9022d floating point infinite loop removed from imperas tests Katherine Parry 2021-05-18 10:42:51 -0400
  • 2feb9309bb script for running make and logging output bbracker 2021-05-17 22:12:18 -0400
  • 02966dd649 changed makefiles so that make stops at bad source code that does not compile bbracker 2021-05-17 21:20:30 -0400
  • f00eb22700 fixed busybear floating point NOP-out feature; restored regression to check 100000 instructions bbracker 2021-05-17 19:25:54 -0400
  • e4c90f503a regression modified to timeout after 10 min \n took Harris\' suggestion for avoiding using ahbliteState package in busybear testbench bbracker 2021-05-17 18:44:47 -0400
  • 9901f54b15 Deleted vish_stacktrace David Harris 2021-05-17 18:39:01 -0400
  • 4370699f3d Started MSTATUS tests David Harris 2021-05-17 18:37:56 -0400
  • e808b06b82 Forgot initialization config for div - apologies James E. Stine 2021-05-17 17:12:27 -0500
  • b818ce608a commit ehedenberg coremark Elizabeth Hedenberg 2021-05-17 18:00:47 -0400
  • 752fefd870 coremark commit ehedenberg final Elizabeth Hedenberg 2021-05-17 17:52:22 -0400
  • 5506efc115 Add 32/64-bit shifter for update to shifter block James E. Stine 2021-05-17 17:02:13 -0500
  • 3d3e3434f6 Cleanup of regression James E. Stine 2021-05-17 16:58:15 -0500
  • daf780b9c2 Mod Imperas Testbench for updated Div/Rem James E. Stine 2021-05-17 16:56:30 -0500
  • 865b3ee219 Updates on Divide - pushed in working version of DIV64U for Divide and REmainder. Will do 32-bit version tomorrow as well as Signed version James E. Stine 2021-05-17 16:48:51 -0500
  • b9e099d53c Fix comment Thomas Fleming 2021-05-14 08:06:07 -0400
  • 6aa04af38d Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main Thomas Fleming 2021-05-14 07:40:08 -0400
  • ea4e76938e Remove busy-mmu and fix missing signal Thomas Fleming 2021-05-14 07:14:20 -0400
  • e27bc1cbf7 Clean up MMU code Thomas Fleming 2021-05-14 07:12:32 -0400
  • 170f072b52 pushing coremark to main branch Elizabeth Hedenberg 2021-05-06 17:45:53 -0400
  • fc69a0cac6 coremark integration into main Elizabeth Hedenberg 2021-05-06 03:47:22 -0400
  • 041149eaf7 Minor fixes in regression Jarred Allen 2021-05-09 13:57:09 -0400
  • c7f400262c Fix bug in regression script Jarred Allen 2021-05-06 12:56:57 -0400
  • e3624ab2e6 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main Domenico Ottolia 2021-05-04 20:22:31 -0400
  • 88ab07d456 Forgot to add csr permission tests to testbench Domenico Ottolia 2021-05-04 20:20:22 -0400
  • be029ba02c Clean up regression script and document it Jarred Allen 2021-05-04 18:58:23 -0400
  • 682bc7b58e Added mip tests to testbench ushakya22 2021-05-04 15:36:06 -0400
  • 1ec6ad14f6 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main Thomas Fleming 2021-05-04 15:22:21 -0400
  • 8a7fc959eb small synthesis fixes bbracker 2021-05-04 15:21:01 -0400
  • 19ac77d3fa Fix compiler warning in PMP checker Thomas Fleming 2021-05-04 15:18:08 -0400
  • 8398e653dd Re-add medeleg tests to testbench Domenico Ottolia 2021-05-04 14:42:20 -0400
  • a03a63a5c7 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main Ross Thompson 2021-05-04 13:04:20 -0500
  • 21acc45121 Fixed synthesis bug with icache valid bit. Ross Thompson 2021-05-04 13:03:08 -0500
  • 2e225bd756 Updated CSR tests ushakya22 2021-05-04 13:48:47 -0400
  • 52e4c49bbb Fixed icache pcmux control for handling miss spill miss. Ross Thompson 2021-05-04 11:05:01 -0500
  • 44ea58b771 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main Thomas Fleming 2021-05-04 03:14:38 -0400
  • 3a3c88f5b1 Fix bug in PMP checker Thomas Fleming 2021-05-04 03:14:07 -0400
  • 46f20745d7 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main ushakya22 2021-05-04 02:22:17 -0400
  • b805b98a8c Added MIE tests to testbench ushakya22 2021-05-04 02:22:01 -0400
  • c9e5af30fa Disable PMP checker to fix test loops Thomas Fleming 2021-05-04 01:56:05 -0400
  • 1673ad6e27 Minor tweaks to mcause & scause tests Domenico Ottolia 2021-05-04 01:33:49 -0400
  • 45b0af497c Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main David Harris 2021-05-04 01:19:57 -0400
  • d68fe44446 Fixed testbench to produce error when signature.output doesn't exist David Harris 2021-05-04 01:19:44 -0400
  • 41a19153cc Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main Thomas Fleming 2021-05-04 01:14:13 -0400
  • 67c7bfe34d Use correct begin_signature for rv64p/MCAUSE and rv64p/SCAUSE Domenico Ottolia 2021-05-04 01:04:12 -0400
  • 09836bae64 Removed WALLY-ADD and WALLY-SUB from rv6rp Makefrag that was causing make to break David Harris 2021-05-04 00:40:15 -0400
  • 973f32da47 Fix 32 bit privileged tests!!! Domenico Ottolia 2021-05-04 00:16:19 -0400