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  • b459d0cc80 changed parsedCSRs2] to parsedCSRs bbracker 2021-06-17 05:18:14 -0400
  • c4983f4388 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main bbracker 2021-06-17 00:50:14 -0400
  • 6625f74a85 still not sure if QEMU workaround is correct, but here is all linux progress so far bbracker 2021-06-17 00:50:02 -0400
  • 33199d2f38 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main Kip Macsai-Goren 2021-06-16 17:37:40 -0400
  • 7b98e7aa2f mcause test fixes and s-mode interrupt bugfix bbracker 2021-06-16 17:37:08 -0400
  • 3b9ecc8275 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main bbracker 2021-06-16 16:17:53 -0400
  • f99c91553f chmod +x'd privileged testgen scripts bracker 2021-06-16 10:28:57 -0500
  • 9c883054c7 fixed incorrect expectation fof CLINT spec bbracker 2021-06-15 19:24:24 -0400
  • 7df01d1f68 removed example page table file. no longer needed. Kip Macsai-Goren 2021-06-15 18:14:01 -0400
  • afdcead5a9 Added page tables to MMU tests David Harris 2021-06-15 17:54:13 -0400
  • 9330c6091a added page table example file, continued work on mmu test Kip Macsai-Goren 2021-06-15 16:13:37 -0400
  • 5cfb9d489a Started WALLY-MMU David Harris 2021-06-15 11:52:16 -0400
  • 16e5e920b8 whoops forgot RV32 bbracker 2021-06-15 11:33:01 -0400
  • 8298c0959d apply changes to privileged tests bbracker 2021-06-15 11:32:10 -0400
  • cd00e04943 Merge remote-tracking branch 'origin/fixPrivTests' into main bbracker 2021-06-15 09:57:46 -0400
  • 4177f4f148 Updated FMA Katherine Parry 2021-06-14 13:42:53 -0400
  • c6ff11c22e disabled Verilator WIDTH warnings in ICCacheCntrl David Harris 2021-06-12 19:50:06 -0400
  • 294f01cbd8 fixed the mtime register. Ross Thompson 2021-06-11 13:50:13 -0500
  • 11c88c15d5 Put repository of fpdivsqrt with RTL-based adder instead of structural implementation James E. Stine 2021-06-11 14:35:22 -0400
  • 8794bf1afa attempt no 1: just change out x28s for x31s bracker 2021-06-11 12:39:28 -0500
  • 49b5fa3994 Reverted MIDELEG and MEDELEG to XLEN so busybear passes David Harris 2021-06-10 23:47:32 -0400
  • e41a87be23 Restored counter events David Harris 2021-06-10 11:18:58 -0400
  • d386929c0e Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main David Harris 2021-06-10 10:47:55 -0400
  • 802238643a Removed two cycles of latency from the DTIM David Harris 2021-06-10 10:30:24 -0400
  • f272cd46d8 peripheral lint fixes bbracker 2021-06-10 10:19:10 -0400
  • d4aeb1c387 merge bbracker 2021-06-10 10:03:01 -0400
  • 0321d74562 attempt to fix regression by adding PMP_ENTRIES to configs bbracker 2021-06-10 09:59:26 -0400
  • d9022551c2 buildroot progress -- able to mimic GDB output bbracker 2021-06-10 09:58:20 -0400
  • 79e798a641 UART improved and added more reg read side effects bbracker 2021-06-10 09:53:48 -0400
  • 3e8026dc21 Configurable number of performance counters David Harris 2021-06-10 09:41:26 -0400
  • 75870a16d7 Restored PCCorrectE declaration in IFU David Harris 2021-06-09 21:09:16 -0400
  • a2c054d0d2 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main David Harris 2021-06-09 21:03:16 -0400
  • 0ffbd03139 More verilator fixes, but bpred is broken David Harris 2021-06-09 21:03:03 -0400
  • c7e57aeb1a removed verilator lint_off WIDTH David Harris 2021-06-09 21:01:44 -0400
  • 01d6ca1e2a Fixed lint WIDTH errors David Harris 2021-06-09 20:58:20 -0400
  • 75257f2ab2 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main bbracker 2021-06-09 15:14:49 -0400
  • 449ac22ecf log only half of bootmem for memory map convenience -- works ok for now because bootmem is half empty bbracker 2021-06-09 15:14:42 -0400
  • 2952550db7 More PMP entries David Harris 2021-06-08 15:33:06 -0400
  • 90e5781471 Start to parameterize number of PMP Entries David Harris 2021-06-08 15:29:22 -0400
  • a95a7a7b82 working version with new mmu comments, old boottim values Kip Macsai-Goren 2021-06-08 15:20:25 -0400
  • 2155cb2e91 merge of reverted main into up to date main Kip Macsai-Goren 2021-06-08 14:57:43 -0400
  • 361c71c5e9 reverted to working version with new mmu comments Kip Macsai-Goren 2021-06-08 14:56:00 -0400
  • b613f46c2d Resized BOOT TIM to 1 KB David Harris 2021-06-08 14:04:32 -0400
  • aab7bd94f7 Merge small mmu changes into main Kip Macsai-Goren 2021-06-08 14:00:26 -0400
  • d6f47d5917 making mmu branch line up with main Kip Macsai-Goren 2021-06-08 13:59:03 -0400
  • e209dbcf50 some cleanup of signals, not done yet Kip Macsai-Goren 2021-06-08 13:39:32 -0400
  • cc91c774a6 Ah big ole merge! Passes sim-wally-batch and linting, so should be fine bbracker 2021-06-08 12:41:25 -0400
  • e7e4105931 * GPIO comprehensive testing * MEPC more aware if M stage has actually committed * UART interrupt testing progress * UART added read IIR side effect of lowering THRE intr bbracker 2021-06-08 12:32:46 -0400
  • 49515245d9 remove redundant decodes, fixed mmu logic ins/outs Kip Macsai-Goren 2021-06-07 19:23:30 -0400
  • 1e174a8244 got rid of some underscores in filenames, modules Kip Macsai-Goren 2021-06-07 18:54:05 -0400
  • c96695b1b6 implemented simpler page mixers, cleaned up a bit Kip Macsai-Goren 2021-06-07 18:32:34 -0400
  • b27abc53e8 began updating cam line to reduce muxes, confusion Kip Macsai-Goren 2021-06-07 17:03:31 -0400
  • 6a63ad04d2 regression working partially done page mask Kip Macsai-Goren 2021-06-07 17:02:31 -0400
  • 9efbffdee5 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main David Harris 2021-06-07 16:14:13 -0400
  • 43a690dc42 Simplified superpage matching David Harris 2021-06-07 16:11:28 -0400
  • 0acf665a8b lint is clean Katherine Parry 2021-06-07 14:22:54 -0400
  • 28c6d60150 temporarily removing buildroot from regression until it is regenerated bbracker 2021-06-07 13:20:50 -0400
  • 2ae5ca19b5 Continued merge David Harris 2021-06-07 12:49:47 -0400
  • ff62000e2c Second attept to commit refactoring config files David Harris 2021-06-07 12:37:46 -0400
  • dc0b19dfaa Merge difficulties David Harris 2021-06-07 09:50:23 -0400
  • d5ec797ba4 Refactored configuration files and renamed testbench-busybear to testbench-linux David Harris 2021-06-07 09:46:52 -0400
  • 75a6097467 fixed lint warnings for fpu and lzd Katherine Parry 2021-06-05 12:06:33 -0400
  • 49200bd922 Cleaned up some unused signals Kip Macsai-Goren 2021-06-04 21:04:19 -0400
  • 22e8e06ac7 moved privilege dfinitions into wally-constants, upgraded relevant includes Kip Macsai-Goren 2021-06-04 17:55:07 -0400
  • 037aa6fa89 Merge branch 'mmu' into main Kip Macsai-Goren 2021-06-04 17:07:56 -0400
  • 3493027bf5 added shared constants file list of includes Kip Macsai-Goren 2021-06-04 17:05:47 -0400
  • 1ae529c450 restructured so that pma/pmp are a part of mmu Kip Macsai-Goren 2021-06-04 17:05:07 -0400
  • 41a1e6112a Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main Ross Thompson 2021-06-04 15:16:39 -0500
  • 7406e33b61 Continued I-Cache cleanup. Removed strange mux on InstrRawD along with the select logic. Ross Thompson 2021-06-04 15:14:05 -0500
  • 191f7e61fd Moved I-Cache offset selection mux to icache.sv (top level). When we switch to set associative this is will be more efficient. Ross Thompson 2021-06-04 13:45:08 -0500
  • e0d0fdd708 Cleaned up the I-Cache memory. Ross Thompson 2021-06-04 13:36:06 -0500
  • fc65aedbd6 Double-precision FMA instructions Katherine Parry 2021-06-04 14:00:11 -0400
  • fdef8df76b Reorganized the icache names. Ross Thompson 2021-06-04 12:41:02 -0500
  • 7c44f19925 Relocated the icache to the cache directoy. Ross Thompson 2021-06-04 12:23:46 -0500
  • 21b1145bdf Added special tests for checking the accuracy of global and gshare branch predictors. Ross Thompson 2021-06-04 11:01:54 -0500
  • a26bf37be8 Started MMU David Harris 2021-06-04 11:59:14 -0400
  • f55af8eb1f updated isa extensions for simple branch predictor test. Ross Thompson 2021-06-04 10:41:21 -0500
  • 4f71964529 Fixed RV32 MMU constants David Harris 2021-06-04 09:15:42 -0400
  • 0674f5506e moved shared constants to a shared directory David Harris 2021-06-03 22:41:30 -0400
  • 8fb2ee6e86 added support for sv48 and some docs on how to use these files Kip Macsai-Goren 2021-06-03 14:32:12 -0400
  • 1ea9b94cf1 added tests for SV48 and translation off with vmem Kip Macsai-Goren 2021-06-03 14:28:52 -0400
  • ad3b103a86 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main bbracker 2021-06-03 10:03:26 -0400
  • 4e765ee1c5 expanded GPIO testing and caught small GPIO bug bbracker 2021-06-03 10:03:09 -0400
  • a7e15f4c23 reached a good stopping point on buildroot progress; parse_qemu.py has been rewritten for readability and QEMU MMU failure workaround bbracker 2021-06-03 10:00:16 -0400
  • e50a1ef5e4 Fixed a few lint errors, clock gater was wrong, missing signal definitions in branch predictor. Ross Thompson 2021-06-02 09:33:24 -0500
  • a683dd7fde Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main bbracker 2021-06-02 10:03:23 -0400
  • 2c77a13c08 fixed InstrValid signals and implemented less costly MEPC loading bbracker 2021-06-02 10:03:19 -0400
  • 5187574e8a implemented Sv48. Kip Macsai-Goren 2021-06-01 17:50:37 -0400
  • 40cfa86935 Edited and added constants to support SV48 Kip Macsai-Goren 2021-06-01 17:49:45 -0400
  • eba7ce64f5 delete div.bak James E. Stine 2021-06-01 17:39:54 -0400
  • babcea195a Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main Ross Thompson 2021-06-01 15:20:37 -0500
  • 0670c57fd2 The clock gater was not implemented correctly. Now it is level sensitive to a low clock. Ross Thompson 2021-06-01 15:05:22 -0500
  • 564d7c4adb Minor cosmetic update to fpu.sv James E. Stine 2021-06-01 15:45:32 -0400
  • 2eeb12c674 Updates to muldiv.sv for 32-bit div/rem James E. Stine 2021-06-01 15:31:07 -0400
  • fe22fd2db8 added clock gater to floating point divider to speed up simulation time. Ross Thompson 2021-06-01 13:46:21 -0500
  • 7f1653f073 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main Ross Thompson 2021-06-01 12:42:21 -0500
  • 997c13a521 Forgot to include the new gshare predictor file. Ross Thompson 2021-06-01 12:41:48 -0500
  • fac2431add Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main Kip Macsai-Goren 2021-06-01 13:20:39 -0400
  • ab509614bb Changed to bp config to use gshare. Ross Thompson 2021-06-01 12:14:58 -0500
  • 89ad4477e4 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main Ross Thompson 2021-06-01 11:33:12 -0500