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  • 77efcad15b Changed names of address in caches. Removed old cache files. Ross Thompson 2022-01-05 22:19:36 -0600
  • 5a2ae561a7 Updates to support fpga. Ross Thompson 2022-01-05 18:07:23 -0600
  • 3517db6b64 Fixed xilinx synth error with $error in extend.sv Ross Thompson 2022-01-05 17:48:08 -0600
  • 1556fb967d fixed 32 vs 64 bit copying error Kip Macsai-Goren 2022-01-05 23:14:03 +0000
  • fb3207fc72 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main Ross Thompson 2022-01-05 16:57:29 -0600
  • 8d33bf0b4a Slower but correct implementation of flush. Ross Thompson 2022-01-05 16:57:22 -0600
  • e33db012ba Reinstated many arch f/d tests that had failed because of memfile issues David Harris 2022-01-05 22:44:10 +0000
  • 31067c8e7d Restored many of the arch32f and arch64d that had been failing because of memfile issues David Harris 2022-01-05 22:23:46 +0000
  • 643732b552 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main David Harris 2022-01-05 22:10:50 +0000
  • e8780878b6 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main Kip Macsai-Goren 2022-01-05 22:10:37 +0000
  • 30c1ab5213 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main David Harris 2022-01-05 22:10:33 +0000
  • 355efda9bc Replaced exe2memfile with SiFive elf2hex David Harris 2022-01-05 22:10:26 +0000
  • 172b6190f4 updated pma tests for simpler test lib Kip Macsai-Goren 2022-01-05 22:10:12 +0000
  • 980bc8067a Added the config file to the outputs of synth kipmacsaigoren 2021-12-03 11:57:16 -0600
  • bf062e2ed7 updated tests to make correctly with output verification Kip Macsai-Goren 2022-01-05 21:43:15 +0000
  • 4efe6813dd allowed option for tests to make without spike simulation. added postverify back in for outputs Kip Macsai-Goren 2022-01-05 21:17:54 +0000
  • 1a9de1fae5 updated pma tests to match simpler test library. They don't pass regression yet Kip Macsai-Goren 2022-01-05 21:13:40 +0000
  • fb8984c8cf Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main Kip Macsai-Goren 2022-01-05 20:17:52 +0000
  • 75788dd9c2 Changes to wave file. Ross Thompson 2022-01-05 14:16:59 -0600
  • bd901cd125 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main Ross Thompson 2022-01-05 14:15:27 -0600
  • 49eea2add5 Fixed bug with flush dirty not cleared in the correct cache line. Ross Thompson 2022-01-05 14:14:01 -0600
  • 20b13a4895 Update README.md davidharrishmc 2022-01-05 11:29:54 -0800
  • 7abddf8719 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main Kip Macsai-Goren 2022-01-05 18:38:29 +0000
  • 64b4981ca1 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main James E. Stine 2022-01-05 10:44:28 -0600
  • 17e9ff4610 Add script to generate memfile using elf2hex James E. Stine 2022-01-05 10:44:01 -0600
  • 85fa620cfb Finished removing generate statements David Harris 2022-01-05 16:41:17 +0000
  • 32590d484c Removed more generate statements David Harris 2022-01-05 16:25:08 +0000
  • f04856ee94 Removed more generate statements David Harris 2022-01-05 16:01:03 +0000
  • c1d6550ccb Removed generate statements David Harris 2022-01-05 14:35:25 +0000
  • f89c1d91dc Renamed most signals inside cache.sv so they are agnostic to i or d. Ross Thompson 2022-01-04 23:52:42 -0600
  • 9eda7c12bd the i and d caches now share common verilog. Ross Thompson 2022-01-04 23:40:37 -0600
  • b06c3b8acd parameterized the caches with the goal of using common rtl for both i and d caches. Ross Thompson 2022-01-04 22:40:51 -0600
  • 06168e67e4 Switched block for line in caches. Ross Thompson 2022-01-04 22:08:18 -0600
  • d94a1c6404 Fixed bug where last line of dcache was not written back to memory on dcache flush. Ross Thompson 2022-01-04 21:55:48 -0600
  • 0dd61a57da Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main Ross Thompson 2022-01-04 18:41:52 -0600
  • 3c3c6d0fe8 Fixed dcache flush. Ross Thompson 2022-01-04 18:40:58 -0600
  • 08e6a10480 Removed imperas mmu tests; using wallypriv instead David Harris 2022-01-04 23:14:53 +0000
  • 17b9143d10 cleaned up Imperas tests to pass make Kip Macsai-Goren 2022-01-04 21:32:21 +0000
  • 87ba45ce36 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main Kip Macsai-Goren 2022-01-04 21:30:51 +0000
  • 0ee4e03cd6 fixed arch tests to pass make, added 32 bit tests, addded all make-passing tests to tests.vh. Kip Macsai-Goren 2022-01-04 21:30:38 +0000
  • 57daff45c8 Fixed bad address for F/fmsub_b18-01 David Harris 2022-01-04 21:04:06 +0000
  • ad3ee6bc08 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main Kip Macsai-Goren 2022-01-04 20:58:08 +0000
  • 1f07470477 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main David Harris 2022-01-04 19:47:51 +0000
  • b36ace221e Renamed wally-pipelined to pipelined David Harris 2022-01-04 19:47:41 +0000
  • d1709e98d2 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main Kip Macsai-Goren 2022-01-04 18:16:46 +0000
  • f3a300738f Added mmu tests to regression-wally. imperas64mmu passes but imperas32mmu does not. Ross Thompson 2022-01-04 11:13:36 -0600
  • 7ac412eb8e Modified dcache to ensure nontranslated index is used. Ross Thompson 2022-01-04 10:53:53 -0600
  • 9ad44e3e97 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main Kip Macsai-Goren 2022-01-04 06:38:28 +0000
  • 1ea267cab5 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main Ross Thompson 2022-01-03 23:49:28 -0600
  • 08b439b9e9 Fixed icache stalling cpu when doing an uncached operation. Ross Thompson 2022-01-03 23:49:19 -0600
  • cc0409b9d6 update 64 bit tests to make make work correctly and general cleanup Kip Macsai-Goren 2022-01-04 05:02:33 +0000
  • cbe255230e Update 32 bit memory tests to make make work correcttly and generally cleanup Kip Macsai-Goren 2022-01-04 04:59:47 +0000
  • a74b0b8f56 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main Kip Macsai-Goren 2022-01-04 04:55:36 +0000
  • 4b4aa11684 Reordered inputs/outputs in caches. Ross Thompson 2022-01-03 22:52:50 -0600
  • fa39de9cef Added generate around the spill logic so it is only used if supporting compressed instructions. Ross Thompson 2022-01-03 22:23:04 -0600
  • 36451bbd15 Minor improvement to icache. Ross Thompson 2022-01-03 22:00:35 -0600
  • a130c03478 More Icache clean up. Ross Thompson 2022-01-03 21:22:34 -0600
  • c2a9b3bc79 Major icache cleanup. Ross Thompson 2022-01-03 21:12:17 -0600
  • 5a438a9498 Removed spill support from icache. Ross Thompson 2022-01-03 21:03:02 -0600
  • 697717707f The ifu now directly supports compressed without the icache providing the implemenation. The icache still constains all the orignal muxing logic to handle spills. This should be removed. Ross Thompson 2022-01-03 20:49:47 -0600
  • b7b9e3bd55 Almost working compressed instructions with compressed detection and processing in ifu rather than icache. Ross Thompson 2022-01-03 18:10:15 -0600
  • 3adc0d43e7 Prepared the ifu and icache for moving spills to ifu. Ross Thompson 2022-01-03 17:00:50 -0600
  • 35c5b9ad50 Fixed bug with the icache. Ross Thompson 2022-01-03 15:55:19 -0600
  • e0c310fea7 Fixed a bug where the instruction fetch got out of sync with the icache. Ross Thompson 2022-01-03 13:27:15 -0600
  • d909e8f371 Replaced && and || with & and | in non-fp files per new style guidelines David Harris 2022-01-02 21:47:21 +0000
  • 9693110857 Started adding asynchronous TIMECLK for CLINT David Harris 2022-01-02 21:18:16 +0000
  • 9d4e1671c9 some errors in FP ArchTests fixed Katherine Parry 2022-01-01 23:50:23 +0000
  • 8d6c48cfb1 Removed .* from MMU. David Harris 2021-12-31 07:19:51 +0000
  • 41052178ce Removed .* from CSRs David Harris 2021-12-31 07:11:03 +0000
  • 470bb6ed4d Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main David Harris 2021-12-31 06:40:25 +0000
  • 9f24b4c969 Simplified performance counters David Harris 2021-12-31 06:40:21 +0000
  • b146c71b14 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main Ross Thompson 2021-12-30 18:10:36 -0600
  • b6fbc4a1e3 Added mux to select between uncache instruction requests and cached instructions requests. Cacheless design almost works with the exception of compressed instructions. Ross Thompson 2021-12-30 18:09:37 -0600
  • 58ef91c94b Fixed wave.do. Ross Thompson 2021-12-30 17:57:07 -0600
  • 5904bc68c7 Patched up the linux-wave.do file. Ross Thompson 2021-12-30 17:53:43 -0600
  • 42df98bc6d Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main David Harris 2021-12-30 23:40:02 +0000
  • b96439dd73 Fixes to counters; buildroot still broken David Harris 2021-12-30 23:39:59 +0000
  • 8e4467654a Working without dcache. Ross Thompson 2021-12-30 16:01:31 -0600
  • 91f67f19a7 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main Ross Thompson 2021-12-30 15:52:15 -0600
  • 6c45da022b Progress on non dcache mode working. Ross Thompson 2021-12-30 15:51:07 -0600
  • 4f052b1ab5 Moved SDC folder into uncore David Harris 2021-12-30 21:38:24 +0000
  • 9136b1fd73 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main Ross Thompson 2021-12-30 15:26:41 -0600
  • 6b59c03d1b No dcache now supported. Does not pass regression tests however. Ross Thompson 2021-12-30 15:26:32 -0600
  • 347896064d Removed unnecessary generate inside hptw David Harris 2021-12-30 21:21:00 +0000
  • 8225f85b86 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main David Harris 2021-12-30 21:15:00 +0000
  • 7847ff33fc Removed carry-save multiplier option from muldiv David Harris 2021-12-30 21:14:57 +0000
  • c79e14fec5 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main Ross Thompson 2021-12-30 14:56:24 -0600
  • b6c9d01f8b Separated the icache from the bus fetching logic. I was able to share the same fsm between the lsu and ifu. Ross Thompson 2021-12-30 14:56:17 -0600
  • 2327f4b6bf Added names to generate blocks David Harris 2021-12-30 20:55:48 +0000
  • 86514a6a23 icache separated from bus fetch fsm. Does not work yet. Ross Thompson 2021-12-30 14:23:05 -0600
  • 41db2743f5 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main Kip Macsai-Goren 2021-12-30 17:32:03 +0000
  • 028a876a4e erge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main David Harris 2021-12-30 17:22:22 +0000
  • d7653dedee Added wally-riscv-arch-test MMU tests and removed imperas MMU tests from regresssion David Harris 2021-12-30 17:22:18 +0000
  • bed7794a18 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main Ross Thompson 2021-12-30 11:01:22 -0600
  • 9bcb105aa4 Changed names of Icache signals. Ross Thompson 2021-12-30 11:01:11 -0600
  • 5a9269591b Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main David Harris 2021-12-30 16:49:36 +0000
  • 9ab4ecdd16 Fixed page table entreis so WALLY-MMU-SV32, SV39, SV48 now run David Harris 2021-12-30 16:46:19 +0000
  • a37c7515bd Icache now works with any sized cache line a power of 2, greater than or equal to 32. Ross Thompson 2021-12-30 10:37:57 -0600
  • d50a65720d More name cleanup in caches. Ross Thompson 2021-12-30 09:18:16 -0600
  • 077bc35e10 Updated lsu so it is possible to condictionally implement dcache or passthrough to ebu. Ross Thompson 2021-12-29 22:24:37 -0600